Method and apparatus for a low noise JFET device on a...

Details Method and apparatus for a low noise JFET device on a... Method and apparatus for a low noise JFET device on a...

2008-05-27

2008-05-27

Pham, Hoai v (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S272000, C257S274000, C257SE29265

Reexamination Certificate

active

07378688

ABSTRACT:
A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.

REFERENCES:
patent: 3999207 (1976-12-01), Arai

Affiliated with

Also associated with

Rating

Method and apparatus for a low noise JFET device on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for a low noise JFET device on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a low noise JFET device on a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2760655