Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-06-30
2003-11-11
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S536000, C257S364000
Reexamination Certificate
active
06646324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of semiconductor circuit design and processing and more particularly to design of buffers suitable for use with transmission line conductors associated with integrated circuits.
2. Description of the Related Art
In many environments in which semiconductor devices are used, the conductors used to link the various devices behave in a manner similar to a transmission line.
FIG. 1A
illustrates a prior art transmission line environment. Buffer
110
drives transmission line
120
, which is terminated to ground by termination impedance
130
. Termination impedance
130
and buffer
110
preferably have the same impedance Z
0
. With such a matched impedance situation, reflections are minimized leading to enhanced signal quality.
It is common to use resistive termination for buses on printed circuit boards, and many semiconductor devices are mounted in packaged form on printed circuit boards. Resistors have a well-known voltage transfer curve (IV curve). Ideally, a resistor has a linear voltage transfer curve, and a typical resistor may be assumed to have an ideal or linear voltage transfer curve. However, the buffers contained within semiconductor devices (such as buffer
110
) rarely have a linear voltage transfer curve.
FIG. 1B
illustrates a voltage transfer curve plot for various circuit elements. In particular, the straight line marked R
ideal
represents the linear voltage transfer curve of a resistor and the curved lines represent voltage transfer curves for an insulated gate FET device. Moreover, the dashed lines R
ac1
and R
ac2
represent the slope of the IV curve for the insulated gate FET at two regions, and it will be apparent that the difference in slope between R
ac1
and R
ac2
is significant. An insulated gate FET biased in a certain operational area may be expected to behave as a resistor for small deviations from the bias point (small signals). R
ac1
and R
ac2
may represent the resistance of an insulated gate FET for small signals when biased at the points where the corresponding IV curve of the insulated gate FET intersects those lines. The nonlinear MOS IV characteristics can result in imperfect termination, thereby increasing inter-symbol interference and degrading signal quality.
It is recognized that a combination of the insulated gate FET and an additional resistor (such as an off-chip series resistor for example) may achieve a more linear IV characteristic. However, this requires an additional component and corresponding opportunities for yield loss or variation in the circuitry. Similarly, a resistor may be formed on-chip between the bond pad and the insulated gate FET structure (or between the insulated gate FET structure and a power/ground rail). However, this may also require additional processing steps, may use up area that must be dedicated at the edge of the device, and may result in additional constraints on the overall design of the device.
SUMMARY OF THE INVENTION
A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.
REFERENCES:
patent: 5493142 (1996-02-01), Randazzo et al.
patent: 5498892 (1996-03-01), Walker et al.
patent: 6100127 (2000-08-01), Wu
Chapter 6 “ESD and I/O Interaction,” Basic ESD and I/O Design, Sanjay Dabral and Timothy Maloney of Intel Corporation, Santa Clara, California, John Wiley & Sons, Inc. 1998, pp. 218-245.
Chapter 2 “CMOS Technology,” CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, Oxford University Press 1987, pp. 29-95.
Chapters 8-12 of Semiconductor Devices Physics and Technology, John Wiley & Sons, Bell Telephone Laboratories, Inc. 1985, pp. 301-506.
Dabral Sanjay
Seshan Krishna
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Perkins Pamela E
Zarabian Amir
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