Oscillators – With synchronizing – triggering or pulsing circuits – Triggering or pulsing
Reexamination Certificate
2000-04-25
2003-10-14
Kinkead, Arnold (Department: 2817)
Oscillators
With synchronizing, triggering or pulsing circuits
Triggering or pulsing
C331S111000, C331S074000, C331S03600C, C331S172000
Reexamination Certificate
active
06633203
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to oscillators and more particularly to gated oscillators.
Oscillators have a wide range of uses. For example, microprocessor operation is synchronized by the periodic timing signals provided by an oscillator. Digital tachometers and digital speedometers in an automobile require a precision reference to provide accurate read-outs. Medical devices such as pacemakers require an accurate pulse generator to ensure proper rhythmic stimulation of the heart.
A gated oscillator is an oscillator that starts or stops oscillating by an enabling signal. In a conventional gated oscillator, such as the one disclosed in U.S. Pat. No. 4,365,212, oscillations are produced by periodically charging and discharging a capacitor between first and second voltage levels when the oscillator is enabled. If it is disabled, the oscillations are stopped by preventing the capacitor from periodically charging and discharging.
Let the first voltage level be lower than the second voltage level. If there is no extra circuitry associated with the capacitor, then the capacitor will continue to discharge past the first voltage level toward the lower power supply voltage when the oscillation is stopped. When the oscillator is enabled, a certain amount of time is needed to charge the capacitor from lower power supply voltage to the first voltage level and then to the second voltage level, whereupon oscillatory behavior ensues. The delay in charging the capacitor from the lower power supply voltage to the first voltage level causes the first pulse in the pulse train to be wider than the rest of the pulses. This error is undesirable in applications which require and expect predictable pulse widths. The error can be substantially corrected if extra circuitry is added to prevent the capacitor from discharging past the first voltage level. This, of course, increases the complexity of the gated oscillator circuitry.
Gated oscillators have many applications in digital circuits. In an article entitled “Gated oscillator emulates a flip-flop,” published in the Mar. 16, 1995 issue of EDN Magazine, a gated oscillator circuit is described in a flip-flop configuration. In another article entitled “Oscillator meets three requirements,” published in the Dec. 3, 1998 issue of EDN Magazine, a gated oscillator is described for use in clock circuit as the clocking source in a digital application.
A design that can be used as a gated oscillator is disclosed in U.S. Pat. No. 5,339,053. A shortcoming of this design, however, is that the enable signal and the gated oscillation are mixed at the circuit's output. Additional external circuitry is therefore required to separate the two signals.
A simplistic gated oscillator circuit can be built using an AND logic gate. An enable signal is applied to one of its terminals and a continuous free running oscillator is applied to the other terminal. The output produces the desired gated oscillations. This prior art gated oscillator requires an external continuous free running oscillator. A problem with this design is the inability of the enable signal to synchronize with the free running oscillator, thus producing indeterminate behavior. Another problem is that the free running oscillation fixes the frequency and duty cycle of the gated oscillator output. Yet another is that the free running oscillator is continually running, even when the enable signal is removed. Consequently, there is unnecessary consumption of power.
There is a need, therefore, for digital circuit design using a gated oscillator circuit which requires reduced support circuitry. It is desirable to provide a design which is energy efficient. There is a need for a design which can provide a tunable oscillation frequency. There is a further for a design that can provide a tunable duty cycle of the oscillation. It is also desirable that the design has an ability to synchronize the onset of oscillatory behavior with the enable signal.
SUMMARY OF THE INVENTION
A method for generating pulses in a digital circuit includes providing a circuit having a variable operating point. The circuit is defined by a transfer function characterized by having an unstable operating region bounded by a first stable operating region and a second stable operating region. The circuit produces oscillatory output when its operating point is moved into the unstable region. The circuit produces a non-oscillatory output when its operating point is placed into either of the first and second stable regions. The method further includes forcing the operating point into the unstable region to produce oscillatory output. The method further includes forcing the operating point into one of the stable regions in order to terminate oscillations.
A gated oscillator circuit in accordance with the invention includes a circuit having a transfer function defined by an unstable operating region bounded by a first stable operating region and by a second stable operating region. The transfer function defines a set of operating points. The circuit is adapted to produce oscillatory output when the operating point is positioned in the unstable region. The circuit is further adapted to produce a non-oscillatory output when its operating point is positioned in either of the first and second stable regions. A function generator, which selectively produces an output of a first level and an output of a second level is coupled to the circuit as an input signal. The operating point is forced into the unstable region when the function generator output is at the first level. This level is called an enable signal. The operating point is forced into one of the stable regions when the function generator output is at its second output level. This level is referred to as a disable signal.
Consequently, the invention requires only the application of an enable signal to enable oscillations or a disable signal to terminate oscillations. The inventive circuit is advantageous in that its oscillations start and stop substantially instantaneously. There are no transients between the ON and OFF state of the oscillator. Another advantage is that the period of the first cycle of oscillation during an ON period is the same as the subsequent cycles in that ON period. There is no need for additional supporting circuit elements or special circuits for maintaining standby levels in the capacitor. The circuit does not require any external free running oscillation. The circuit will generate its own oscillation when triggered by the enable signal. The circuit is inherently synchronized with the enable signal. By tuning the circuit parameter, without changing the circuit configuration, the duty cycle and the frequency of oscillation can be varied. The gated oscillation at the output of the circuit is not overlapping with the enable signal and therefore no additional circuit is required to separate them.
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pa
Allen Kenneth R.
Kinkead Arnold
The National University of Singapore
Townsend and Townsend / and Crew LLP
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