Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2006-10-24
2006-10-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S297000
Reexamination Certificate
active
07126405
ABSTRACT:
Methods and Apparatuses for generating and distributing a clock signal between components within a semiconductor chip. According to one embodiment of the invention, a clock generator, distributed over an integrated circuit, includes a plurality of cells each coupled to multiple adjacent ones of the plurality of cells by different clock wires; wherein, for each of the plurality of clock wires, the cell on one end generates the rising edge and the cell on the other end generates the falling edge. According to another embodiment of the invention, an integrated circuit includes a distributed clock generator and a plurality of sets of synchronous logic. The distributed clock generator includes a plurality of cells and a plurality of clock wires. The plurality of clock wires each couple together two of said plurality of cells such that said plurality of cells are coupled together in grid. The plurality of cells, responsive to a mixing of previous clock edges produced by at least certain of said plurality of cells, detect when to produce the next clock edge. The plurality of sets of synchronous logic each have a clock input. Each clock input of each of these sets is coupled to a different one of said plurality of clock wires.
REFERENCES:
patent: 5592127 (1997-01-01), Mizuno
patent: 5640112 (1997-06-01), Goto et al.
patent: 5712883 (1998-01-01), Miller et al.
patent: 5883534 (1999-03-01), Kondoh et al.
patent: 5892373 (1999-04-01), Tupuri et al.
patent: 6037820 (2000-03-01), Ishizaka
patent: 6057724 (2000-05-01), Wann
patent: 6118304 (2000-09-01), Potter et al.
patent: 6191658 (2001-02-01), Fairbanks
patent: 6305001 (2001-10-01), Graef
patent: 6400230 (2002-06-01), Fairbanks
patent: 6531897 (2003-03-01), Milshtein et al.
patent: 6538957 (2003-03-01), Magoshi
patent: 6552589 (2003-04-01), Masleid
patent: 6657502 (2003-12-01), Bushman et al.
Clock Distribution Using Coupled Oscillators (pp. 217-200), I. Galton, D.A. Towne, James J. Rosenberg, H.T. Jensen, Univ. ofCA, Irvine, Harvey Mudd Col., Claremont, CA (1996).
Active GHz Clock Network Using Distributed PLLs (pp. 1553-1560), Vadim Gutnik, Member, IEEE and Anantha P. Chandrakasan, Member, IEEE (2000).
The Distributed Clock Generator (6 pgs)by Scott Fairbanks, Simon Moore, Computer Laboratory, University of Cambridge, UK Dec. 5, 2001.
On the Micro-Architectural Impact of Clock Distribution Using Multiple PLLs (7 pgs), Martin Saint-Lauren, Madhavan Swaminathan and James D. Meindl, Inel Corp., Austin, TX, USA, Georgia Inst. of Tech., Atlanta, GA, USA Sep. 2001.
Blakely , Sokoloff, Taylor & Zafman LLP
Callahan Timothy P.
Fairbanks Scott
Nguyen Hai L.
LandOfFree
Method and apparatus for a distributed clock generator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for a distributed clock generator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for a distributed clock generator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3682942