Method and apparatus for a digital signal processor having a mul

Details Method and apparatus for a digital signal processor having a mul Method and apparatus for a digital signal processor having a mul

1995-04-07

1997-10-07

Shah, Alpesh M.

Boots, shoes, and leggings

3647485, 3642286, 3642328, 3642582, 364DIG1, G06F 738

Patent

active

056758227

ABSTRACT:
A digital signal processor having a multiplierless computation block (140) is accomplished by storing approximations of computed logarithms in memory (160, 162). When two pieces of data (114, 116) are received, the approximate logarithms, or logarithmic data (120, 128), for each of the pieces data are retrieved from memory. The logarithmic data (120, 128) is them summed to produce a resultant (136), wherein the resultant (136) is used to retrieve an inverse logarithmic approximation (180) that is stored in memory (170, 172) in a manner similar to that of the logarithmic approximations. The inverse logarithmic approximation (180) that results closely approximates the product of multiplying, or another arithmetic function, the two pieces of data (114, 116).

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patent: 5337266 (1994-08-01), Arnold
patent: 5359551 (1994-10-01), Pickett
patent: 5365465 (1994-11-01), Larson
patent: 5553012 (1996-09-01), Buss et al.
Motorola, Inc.; "DSP56100 Digital Signal Processor Family Manual"; 1993.

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