Oscillators – Plural oscillators – Parallel connected
Reexamination Certificate
2002-05-21
2003-12-09
Kinkead, Arnold (Department: 2817)
Oscillators
Plural oscillators
Parallel connected
C331S046000, C331S049000, C331S053000, C331S055000, C708S103000, C327S116000, C327S119000, C377S047000
Reexamination Certificate
active
06661298
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to digital circuits and more particularly to clock multiplication circuitry.
A clock multiplication circuit outputs a clock frequency that is a result of an integer multiplication of the input clock frequency. Frequency multiplication has many uses. For example, frequency multiplication allows a microprocessor to carry out instruction execution at different clock rates.
In a conventional clock multiplication circuit, a phase locked loop is used. A phase locked loop typically comprises a phase detection circuit, an amplifier, and a voltage-controlled oscillatory. There has traditionally been reluctance to use phase locked loops, partly because of the complexity of using discrete components to realize such circuits.
Another method to realize a clock multiplication circuit is shown in U.S. Pat. No. 5,107,264. As can be seen in
FIG. 2
of the patent, this circuit requires the use of Q−1 delay circuits to achieve an output whose frequency is a Q multiple of the input clock frequency. A total of Q−1 delayed versions of the low frequency input clock are passed through an edge detector (
36
) which responds to the rising edge of a pulse by producing one high frequency pulse. Since there are Q numbers of low frequency clock with different delay passing through the edge detectors, then Q numbers of high frequency pulse are generated at different times. All these high frequency pulses are combined by an OR gate (
40
) to yield Q clock pulses in response to one low frequency clock at the input.
The number of delay circuits and edge detectors increases as the multiplication factor is increased. Furthermore, when the multiplication factor for the same input clock frequency is changed, besides having to add/remove the delay circuits and edge detectors, the parameters of each delay circuit have to be re-tuned. This process is impractical when Q is large.
There is a need for an improved digital clock multiplication technique.
SUMMARY OF THE INVENTION
A method for frequency multiplication includes producing a first intermediate signal having n/2 oscillations during the first half of one cycle of the input signal and no oscillations during the second half of the cycle. A second signal having no oscillations during the first half cycle and n/2 oscillations during the second half cycle is combined with the first signal to produce the multiplied signal.
In accordance with the invention, the first and second signal are produced by a circuit that is defined by a transfer function characterized by having an unstable operating region bounded by a first stable operating region and a second stable operating region. The circuit produces oscillatory output when its operating point is moved into the unstable region. The circuit produces a non-oscillatory output when its operating point is placed into either of the first and second stable regions. The method further includes forcing the operating point into the unstable region to produce oscillatory output. The method further includes forcing the operating point into one of the stable regions in order to terminate oscillations.
The inventive circuit is advantageous in that its oscillations start and stop substantially instantaneously. There are no transients between the ON and OFF state of the oscillator. Another advantage is that the period of the first cycle of oscillation during an ON period is the same as the subsequent cycles in that ON period. There is no need for additional supporting circuit elements or special circuits for maintaining standby levels in the capacitor. The circuit does not require any external free running oscillation. The circuit will generate its own oscillation when triggered by the enable signal. The circuit is inherently synchronized with the enable signal. By tuning the circuit parameter, without changing the circuit configuration, the duty cycle and the frequency of oscillation can be varied. The gated oscillation at the output of the circuit is not overlapping with the enable signal and therefore no additional circuit is required to separate them.
REFERENCES:
patent: 3129342 (1964-04-01), Kaenel
patent: 3209282 (1965-09-01), Schnitzler
patent: 3239832 (1966-03-01), Renard
patent: 3246256 (1966-04-01), Sommers, Jr.
patent: 3303350 (1967-02-01), Neff et al.
patent: 3312911 (1967-04-01), De Boer
patent: 3387298 (1968-06-01), Kruy
patent: 3527949 (1970-09-01), Huth
patent: 3571753 (1971-03-01), Saunders
patent: 3755696 (1973-08-01), Nicholson et al.
patent: 3761621 (1973-09-01), Vollmeyer et al.
patent: 3846717 (1974-11-01), Fleming
patent: 3967210 (1976-06-01), Aumann
patent: 4028562 (1977-06-01), Zuleeg
patent: 4037252 (1977-07-01), Janssen
patent: 4365212 (1982-12-01), Gentile et al.
patent: 4425647 (1984-01-01), Collins et al.
patent: 4459591 (1984-07-01), Haubner et al.
patent: 4560949 (1985-12-01), Young
patent: 4599549 (1986-07-01), Mutoh et al.
patent: 4641317 (1987-02-01), Fullerton
patent: 4743906 (1988-05-01), Fullerton
patent: 4862160 (1989-08-01), Ekchian et al.
patent: 5012244 (1991-04-01), Wellard et al.
patent: 5107264 (1992-04-01), Novof
patent: 5170274 (1992-12-01), Kuwata et al.
patent: 5237290 (1993-08-01), Banu et al.
patent: 5274375 (1993-12-01), Thompson
patent: 5339053 (1994-08-01), Lux et al.
patent: 5459749 (1995-10-01), Park
patent: 5461643 (1995-10-01), LaRosa et al.
patent: 5532641 (1996-07-01), Balasubramanian et al.
patent: 5539761 (1996-07-01), Golub et al.
patent: 5610907 (1997-03-01), Barrett
patent: 5640427 (1997-06-01), Rainish
patent: 5691723 (1997-11-01), King et al.
patent: 5757301 (1998-05-01), Kuo et al.
patent: 5764702 (1998-06-01), Caiaffa
patent: 5777507 (1998-07-01), Kaminishi et al.
patent: 5789992 (1998-08-01), Moon
patent: 5812081 (1998-09-01), Fullerton
patent: 5832035 (1998-11-01), Fullerton
patent: 5892701 (1999-04-01), Huang et al.
patent: 5901172 (1999-05-01), Fontana et al.
patent: 6023672 (2000-02-01), Ozawa
patent: 6044113 (2000-03-01), Oltean
patent: 6060932 (2000-05-01), Devin
patent: 6087904 (2000-07-01), Wen
patent: 6259390 (2001-07-01), Joe
patent: 6275544 (2001-08-01), Aiello et al.
patent: 6292067 (2001-09-01), Sasabata et al.
patent: 6392498 (2002-05-01), Lye et al.
patent: 94 855 (1973-01-01), None
patent: 2459531 (1976-07-01), None
patent: 2602794 (1977-07-01), None
patent: 19809334 (1999-09-01), None
patent: 1438262 (1966-07-01), None
patent: 11-074766 (1999-03-01), None
patent: WO 00/5987 (2000-02-01), None
patent: 00/05597 (2000-03-01), None
Abell, E., “Gated Oscillator Emulates a Flip-Flop,”EDN Access, pp. 1-2 (1995).
Gallerani, A., “Oscillator Meets Three Requirements,”EDN Access, pp. 119-120 (1995).
Goras et al., “On Linear Inductance- and Capacitance- time Conversions Using NIC- Type Configuration,”IEEE Trans. Ind. Electronics, 40(5):529-531 (1993).
Jakubaschk, V.H., “das Gro&bgr;e Elektronikbastelbuch,” Deutscher Militarverlag, Leipzig, pp. 206-209 (1968).
Keener, J.P., “Analog Circuitry for the van der Pol and FitzHugh—Nagumo Equations,”IEEE, pp. 1011-1015 (1983).
Li et al., “Performance of a Ratio-Threshold Diversity Combining Scheme in FFH/FSK Spread Spectrum Systems in Partial Band Noise Interference,”IEEE, Dept. of Electrical and Computer Engineering, and Communication Research Centre, pp. 0672-0676 (1992).
Li et al., “Maximum-Liklihood Diversity Combining in Partial-Band Noise Interference Channel,”IEEE, Department of Electrical and Computer Engineering, and Communication Research Centre, pp. 507-511 (1993).
Patarasen et al., “Maximum-Liklihood Symbol Synchronization and Detection of OPPM Sequences,”IEEE Transactions on Communications, 42(6):9 (1994).
Sen et al., “Integration of GaAs/A1As Resonant Tunneling Diodes for Digital and Analog Applications with Reduced Circuit Complexity,” (1987).
Tietze et al., “Halbleiter-Schaltungstechnik, Funfte, uberarbeitete Auflage,” Springer-Verlag, Berlin, Heidleberg, New york, pp. 255-258 (1980).
Wang et al., “Image Segmentation Based on Oscillatory Correlation,”Neural Computation, 9:805-836 (1997).
Joe Jurianto
Lye Kin Mun
Allen Kenneth R.
Kinkead Arnold
The National University of Singapore
Townsend and Townsend / and Crew LLP
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