Method and apparatus for a design for test, parallel block write

Details Method and apparatus for a design for test, parallel block write Method and apparatus for a design for test, parallel block write

1996-08-30

1998-04-14

Beausoliel, Jr., Robert W.

Excavating

G11C 2900

Patent

active

057401799

ABSTRACT:
An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

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