Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...
Reexamination Certificate
2007-03-27
2007-03-27
Parker, Kenneth (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With contact or metallization configuration to reduce...
C257S510000, C257S513000, C257SE21577, C438S221000, C438S296000, C438S353000
Reexamination Certificate
active
10745311
ABSTRACT:
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.
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patent: 5965940 (1999-10-01), Juengling
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patent: 2003/0058701 (2003-03-01), Takashima
Juengling, Werner, et al., “Fill Pattern Generation for Spin-On-Glass and Related Self-Planarization Deposition”, U.S. Appl. No. 10/032,877, filed Oct. 24, 2001.
Ireland Philip J.
Juengling Werner
Krazit Stephen M.
Micro)n Technology, Inc.
Nguyen Joseph
Parker Kenneth
Schwegman Lundberg Woessner & Kluth P.A.
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