Method and apparatus for a deposited fill layer

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...

Reexamination Certificate

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C257S510000, C257S513000, C257SE21577, C438S221000, C438S296000, C438S353000

Reexamination Certificate

active

10745311

ABSTRACT:
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

REFERENCES:
patent: 5683075 (1997-11-01), Gaul et al.
patent: 5965940 (1999-10-01), Juengling
patent: 5981384 (1999-11-01), Juengling
patent: 6521969 (2003-02-01), Tomita
patent: 6737723 (2004-05-01), Farrar
patent: 2003/0058701 (2003-03-01), Takashima
Juengling, Werner, et al., “Fill Pattern Generation for Spin-On-Glass and Related Self-Planarization Deposition”, U.S. Appl. No. 10/032,877, filed Oct. 24, 2001.

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