Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-08-29
2003-12-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S508000, C257S513000
Reexamination Certificate
active
06667531
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor wafers and semiconductor devices and their fabrication. Specifically, the invention relates to methods of fabricating layers on a semiconductor wafer, and the semiconductor devices that result from the methods.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are formed using large numbers of complex processing operations to form several layers of devices and electrical connections stacked on top of each other. Isolating layers of dielectric material are needed to electrically isolate semiconductor devices and electrical connecting lines from each other. The dielectric material is typically deposited in lateral spaces between elements such as semiconductor devices and between electrical connections such as trace lines. The dielectric material is also deposited between multiple layers of devices or connections to isolate portions of layers from each other.
FIG. 1
shows an integrated circuit
100
, including a semiconductor substrate
110
. The integrated circuit
100
includes a number of semiconductor devices
120
that are formed on, or within the substrate
110
. Electrical connections such as first electrical connection
130
and second electrical connection
132
are included for interconnecting selected semiconductor devices
120
.
Current fabrication methods utilize a multiple step process to isolate various elements of the integrated circuit
100
as described. A first dielectric layer
150
is included in the multiple step process. The first dielectric layer
150
is shown in
FIG. 1
located over the electrical connections
130
and
132
. The dielectric layer
150
in common configurations is a conformal layer that contacts both a substrate elevation level area
112
and an element elevation level area
114
.
One current technique also utilizes supplemental structures such as structure
140
to minimize the amount of surface area on the substrate
110
that is at the substrate elevation level
112
. However, with the configuration shown in
FIG. 1
, there is still a substantial difference in elevation between the substrate elevation level
112
and the element elevation level
114
. The conformal dielectric layer
150
of the current process does not yield a planar outer surface.
It is desirable to form a substantially planar outer surface so that stacks of layers including subsequent semiconductor devices or electrical connections can be formed as needed. Using the current process, additional dielectric layers such as second dielectric layer
160
are needed to form a substantially planar outer surface
162
. The outer surface
162
is made planar by selecting the second dielectric material and deposition process such that remaining recesses
163
are filled in.
Currently, no process or product exists that forms the substantially planar outer surface
162
in a single processing operation, with a single layer of material. Multiple process operations, while often necessary, are undesirable because of added time and manufacturing cost associated with each additional operation.
A via
170
is further shown in
FIG. 1
, formed through the first dielectric layer
150
and the second dielectric layer
160
. The via
170
is needed when utilizing subsequent device or electrical connection layers, to form an electrical contact that communicates with, for example, the second electrical connection
132
as shown.
The via
170
includes a via width
172
. Because the via
170
passes through both the first dielectric layer
150
and the second dielectric layer
160
in order to reach the second electrical connection
132
, the via has a height that is equal to a thickness
166
. The thickness
166
is equal to a first dielectric layer thickness
152
added to a second dielectric layer thickness
164
. The via
170
has an aspect ratio equal to its height over its width
172
. Due to thickness variations introduced in each deposition operation, there is a large variation in aspect ratios of vias formed after two dielectric depositions. High aspect ratio vias can be difficult to fill with conductive material in later processing operations. Aspect ratio variations are thus undesirable because of the resulting low reliability of high aspect ratio vias.
What is needed is a method of processing a semiconductor wafer to form a semiconductor device or integrated circuit that uses fewer processing steps. What is also needed is a method of processing a semiconductor wafer to form a semiconductor device or integrated circuit that allows more controlled variation of via aspect ratios.
SUMMARY OF THE INVENTION
The above mentioned problems with semiconductor processing and resulting semiconductor devices are addressed by the present invention and will be understood by reading and studying the following specification. Systems, devices and methods are provided for processing a semiconductor wafer using fewer steps. The systems, devices, and methods of the present invention offer fewer processing steps while at the same time providing a planar surface and more reliable vias.
A method of fabricating a semiconductor wafer is provided. The method includes forming a pattern of elements on a semiconductor surface. Forming a pattern of elements includes forming a number of conductive elements on the semiconductor surface, the conductive elements being spaced apart from each other. Spaces between elements of the pattern define a number of trenches with trench axes that are substantially parallel to sides of adjacent elements of the pattern. This method of fabricating a semiconductor wafer further includes designing the pattern to substantially eliminate portions of the pattern where trench axes cross one another.
Other methods are provided that include forming a number of supplemental elements in selected regions on the semiconductor surface adjacent to the number of conductive elements, the supplemental elements being spaced apart from each other and the number of conductive elements. In one embodiment, the number of conductive elements include a number of conductive trace lines. In one embodiment, the number of conductive elements include metal. In one embodiment, the supplemental elements include metal supplemental elements. In one embodiment, the conductive elements and the supplemental elements are concurrently formed. Another embodiment further includes filling the number of trenches with a dielectric material to form a substantially planar surface. One process operation of filling the number of trenches with a dielectric material includes utilizing a spin-on-glass process. Another process operation of filling the number of trenches with a dielectric material includes a chemical vapor deposition (CVD) process. In one embodiment, filling the number of trenches with a dielectric material is accomplished in a single process operation. Methods of forming memory devices and information handling systems are also provided.
An integrated circuit is also provided. The integrated circuit includes a number of semiconductor devices formed on a semiconductor substrate. The integrated circuit also includes a pattern of elements on the semiconductor surface, the pattern including a number of conductive elements operatively coupling selected semiconductor devices to one another on the semiconductor surface, the conductive elements being spaced apart from each other. The pattern also includes a number of supplemental elements in selected regions on the semiconductor surface adjacent to the number of conductive elements, the supplemental elements being spaced apart from each other and the number of conductive elements. Spaces between elements of the pattern define a number of trenches with trench axes that are substantially parallel to sides of adjacent elements of the pattern, wherein no trench axes cross one another.
In one embodiment, the number of semiconductor devices includes a number of transistors. In one embodiment, the dielectric layer includes tetraethylorthosilicate (TEOS). In one embodiment, the dielectric layer includes si
Ireland Philip J.
Juengling Werner
Krazit Stephen M.
Nelms David
Nguyen Thinh T.
Schwegman Lundberg Woessner & Kluth P.A.
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