Method and apparatus for a coherent copy-back buffer in a multip

Details Method and apparatus for a coherent copy-back buffer in a multip Method and apparatus for a coherent copy-back buffer in a multip

1996-07-29

1998-01-13

Chan, Eddie P.

395447, 395470, 395473, 395293, 395299, G06F 1208

Patent

active

057087920

ABSTRACT:
A method and apparatus for maintaining cache coherency in a multiprocessor system having a plurality of processors and a shared main memory. Each of the plurality of processors is coupled to at least one cache unit and a store buffer. The method comprises the steps of writing by a first cache unit to its first store buffer a dirty line when the first cache unit experiences a cache miss; gaining control of the bus by the first cache unit; reading a new line from the share main memory by the first cache unit through the bus; writing the dirty line to the shared main memory if the bus is available to the first cache unit and if not available, the first cache unit checking snooping by a second cache unit from a second processor; comparing an address from the second cache unit with the tag of the dirty line, wherein the tag is stored in content-addressable memory coupled to the store buffer and if there is a hit, then supplying the dirty line to the second cache unit for updating.

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