Method and apparatus for a cache memory with data priority order

Details Method and apparatus for a cache memory with data priority order Method and apparatus for a cache memory with data priority order

1995-10-27

1996-09-10

Kim, Matthew M.

Boots, shoes, and leggings

395472, 395417, 395403, 364DIG1, 36424341, 3642531, 3642557, G06F 1210

Patent

active

055553931

ABSTRACT:
A method and an apparatus for cache lock control are designed for use with a cache memory. The cache memory has divided entries each for storing data and cache lock information. Updating of data in each of the entries of the cache memory is controlled in response to cache priority order information in each of the entries of the cache memory.

REFERENCES:
patent: 4638426 (1987-01-01), Chang et al.
patent: 5029072 (1992-07-01), Moyer et al.
patent: 5163143 (1992-11-01), Culley et al.
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5297270 (1994-03-01), Olson
"Sparc Risc User's Guide" by Cypress Semiconductor, Feb. 1990, pp. 4-18 to 4-19 pp. 4-34 to 4-35.

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