Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-09-17
2003-05-20
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S493000
Reexamination Certificate
active
06567835
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a carry save adder. More specifically, the present invention relates to a carry save adder for use in a multiplier circuit.
2. Description of the Related Art
The earliest processors did not include hardware to perform multiplication. Instead, multiply operations were accomplished by performing sequences of shifts and adds. As technology evolved to provide higher levels of device integration, it became practical to include hardware dedicated to multiplication within the processor. Initially, the multiply hardware improved the performance of multiplication by directly supporting multiply instructions, although not at the processor's best possible speed (i.e., multiplication typically took much longer to perform than addition). Further evolution of processors has led to fully pipelined multipliers, allowing processors to initiate multiply instructions at the same rate as they initiate addition instructions, although in most cases at a greater latency.
While increasing integration levels allow the implementation of fully pipelined multipliers, the need for multiply performance is being driven by the changing nature of compute intensive programs. Today, these programs are typically dominated by algorithms that model aspects of the physical world. For example, audio and video compression involve transforming information into a different domain, such as audio into the frequency domain, and then the removal of unimportant information from the desired data. This is one example of a multiply intensive operation. Future software will likely require even greater multiply performance, for example, the Newton-Raphson technique in implementing the divide operation is growing in popularity and uses a sequence of multiply operations.
Nearly all processors implement multiply using a combination of two techniques: Booth encoding and Wallace trees. The Booth encoding process, which produces a number of partial products, uses one of the two multiplicands to select multiples of the other operand in each pair of bit positions of the first operand. A Wallace tree then sums the partial products to produce an output. Booth encoding and Wallace trees are well known in the art, and are not discussed in detail in this disclosure.
There exists a variety of Booth encoders and Wallace trees that are known in the art. One of the most common Booth encoders generates one of five different multiples of the second operand: 2x, 1x, 0x, −1x or −2x. It is possible to design other types of Booth encoders, but these other designs could not be implemented by simple multiplexers. (E.g., the 1x and 2x multiples are accomplished by simple shifts, while a 3x multiple requires an addition).
A Wallace tree is typically built from 3:2 counter gates or carry-save-adders (CSA) (also known as carry-save-adders). These gates add three bits of identical significance (or weight), and produce a carry of one bit greater significance, and a sum of identical significance to the inputs. The result is that three bits of the input are reduced to two in one CSA level. It is possible to design other forms of CSAs, such as a 7:3 counter described in Metha et al,
High
-
Speed Multiplier Design Using Multi
-
Input Counter and Compressor Circuits
, IEEE 10th Symposium on Computer Architecture (June 1991). These types of counters are typically avoided due to increased complexity, gate count, or an inability to achieve similar performance.
Nearly all of today's CMOS processors are constructed from flip-flop or latch synchronized static logic. New designs are starting to emerge that use combinations of static and dynamic logic, and more aggressive synchronization schemes. For example, Intrinsity, Inc. (formerly known as EVSX, Inc.) has invented a new logic family called N-NARY logic, which can be characterized as a fully-dynamic and self-synchronized logic family. N-NARY logic is more fully described in a copending patent application, U.S. patent application Ser. No. 09/019355, filed Feb. 05, 1998, now U.S. Pat. No. 6,066,965, and titled “Method and Apparatus for a N-NARY logic Circuit Using 1-of-4 Signals”, which is incorporated by reference for all purposes into this disclosure and is referred to as “The N-NARY Patent.” Additionally, the present invention is related to a multiplier built using N-NARY logic that is fully described in a copending patent application, U.S. patent application Ser. No. 09/186843, filed Nov. 05, 1998, now U.S. Pat. No. 6,275,841 and titled “1-of-4 Multiplier”, which is incorporated by reference for all purposes into this disclosure. The present invention incorporates and or modifies N-NARY adders that are described in several copending patent applications, U.S. patent application Ser. No. 09/150720, filed Sep. 10, 1998, now U.S. Pat. No. 6,219,687, and titled “Method and Apparatus for an N-NARY Sum/HPG Gate”, U.S. patent application Ser. No. 09/150829, filed Sep. 10, 1998, now U.S. Pat. No. 6,216,146, and titled “Method and Apparatus for an N-NARY Adder Gate”, and U.S. patent application Ser. No. 09/150575, filed Sep. 10, 1998, now U.S. Pat. No. 6,223,199, and titled “Method and Apparatus for an N-NARY HPG Gate”, all of which are incorporated by reference into this disclosure for all purposes. A greater discussion of capacitance isolation using N-NARY logic can be found in a copending patent application, U.S. patent application Ser. No. 09/209967, filed Dec. 10, 1998, now U.S. Pat. No. 6,124,735, and titled “Method and Apparatus for a N-Nary Logic Circuit Using Capacitance Isolation,” which is incorporated by reference for all purposes into this disclosure. Additionally, a greater discussion of the wire capacitance can be found in a copending patent application, U.S. patent application Ser. No. 09/019278, filed Feb. 05, 1998, titled “Method and Apparatus for a 1-of-N Signal,” which is incorporated by reference for all purposes into this disclosure. And, the reduced power consumption benefits using N-NARY logic can be found in a copending patent application, U.S. patent application Ser. No. 09/209207, filed Dec. 10, 1998, now U.S. Pat. No. 6,107,835, and titled “Operation-Independent Power Consumption,” which is incorporated by reference for all purposes into this disclosure.
The N-NARY logic family supports a variety of 1-of-N signal encodings, including 1-of-4. In 1-of-4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values, as is demonstrated in Table 1. In Table 1, the A
0
and A
1
wires are used to indicate the four possible values for operand A: 00, 01, 10, and 11. Table 1 also shows the decimal value of an encoded 1-of-4 signal corresponding to the two-bit operand value, and the methodology by which the value is encoded using four wires.
TABLE 1
2-bit
N-NARY (1-of-
operand
4) Signal A
N-NARY (1-of-4) Signal A
value
Decimal Value
1-of-4 wires asserted
A
1
A
0
A
A[3]
A[2]
A[1]
A[0]
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
2
0
1
0
0
1
1
3
1
0
0
0
“Traditional” dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, as shown in Table 1, N-NARY logic only requires assertion of one wire. The benefits of N-NARY logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of the N-NARY Patent. All signals in N-NARY logic, including 1-of-4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (0-3 inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a valid 1-of-N signal. Similarly, N-NARY logic requires that a high voltage be asserted on only one wire for all values, even the value for zero (0). A null value (or no wires asserted) means that no valid data is present.
Any one N-NARY logic gate may comprise multiple
Blomgren James S.
Brooks Jeffrey S.
Booth Matthew J.
Booth & Wright LLP
Do Chat C.
Intrinsity, Inc.
Ngo Chuong Dinh
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