Dynamic magnetic information storage or retrieval – General recording or reproducing – Signal switching
Reexamination Certificate
1998-12-16
2002-10-29
Holder, Regina N. (Department: 2651)
Dynamic magnetic information storage or retrieval
General recording or reproducing
Signal switching
C360S046000, C360S067000
Reexamination Certificate
active
06473256
ABSTRACT:
TECNICAL FIELD OF THE INVENTION
The present invention relates to disc drive systems and more particularly for devices for a write to read switching circuit.
BACKGROUND OF THE INVENTION
Magnetic disc drives have read/write heads out of which the write head portion is used for writing data to magnetic discs and the read head portion is used for reading data from the magnetic disc. During a write operation, a write signal is provided to a selected write head from a write control circuit. The write signal represents data to be encoded into the magnetic disc. More particularly, the write head receives encoded digital data from a “channel” circuit. The transitions of the signal received from the channel circuit causes the write current flowing within the write head to reverse direction which in turn, induces a flux reversal in the magnetized material of the medium of the magnetic disc.
During a read operation, the read head senses flux reversals from the magnetic disc. The flux reversals are encoded into magnetic disc during the write operation. Based on the flux reversals, the read head provides a read signal to a read channel. The read circuit amplifies the read signal, and the channel circuit recovers the data. The read circuit then provides the data to a magnetic disc controller for further processing.
Each magnetic disc in a disk drive has a corresponding “head” adjacent to the top and bottom surface of the disc. Thus, there are two heads per stack where N equals the number of disc in a drive. Normally, only one head is active at a given time in order to control these channels. Typically, each channel additionally includes a current path for current to flow to the MR head.
When switching from a write mode when the write circuit is activated to a read mode when a read circuit is activated, a write to read switching circuit is employed to assure that the transitions created by the change from the write mode to the read mode have been eliminated. One of the criterion of a write to read switching circuit is to minimize any delay associated with the write to read switching circuit.
One such write to read switching circuit is illustrated in FIG.
1
. This circuit includes a head
100
, which is connected to a Rmr measurement circuit
122
. The RMR measurement circuit
122
includes a resistor
124
which is coupled to a FET
126
which is coupled to ground. This FET
126
controls the activation of the measurement circuit
122
. However, the FET
126
requires a finite amount of time to switch the measurement circuit
122
and introduces noise to the write to read switching circuit. Additionally, the FET
124
shuts off the current to the Rmr measurement circuit
122
during write mode. However, when going. from write to read, the current begins to flow in the Rmr measurement circuit
122
causing a transient in the head circuit
100
. This results in a longer time for the current to settle in the Rmr measurement circuit
122
causing additional delay in the write to read time.
Additionally,
FIG. 1
illustrates transconductance circuit
114
. The lower corner frequency of the reader F
cf
is set by two poles namely, G
m−c
and low pass filter pole P
LPF
. These multiple poles with a zero results in the read circuit being less stable causing over shoot, and the transient response of the reader circuit is extended. This over shoot causes substantially larger settling time with the reader resulting in poor write to read time.
Additionally, there is a further problem associated with the transconductance circuit
114
. As illustrated in
FIG. 1
, reference voltage generator
118
output a voltage V
ref
to transconductance circuit
114
. The transconductances circuit
114
inputs and references the reference voltage V
ref
with respect to internal ground. In contrast, the external resistor
120
is connected to external ground. As a consequence, when the preamplifier goes from a write to read, there is a transient voltage generated in the internal ground. This will alter the voltage V
ref
which is measured with respect to internal ground. The transient affects the generation of the transconductance circuit
114
. Any change in voltage V
ref
will cause a transient in current I which flows from transconductance circuit
114
to capacitor
116
and to the gate of transistor
102
.
SUMMARY OF THE INVENTION
The present invention includes a write to read switching circuit having a switching time of 200 nano seconds. This is because by the invention, the transients which are generated by switch from the write mode to the read mode are significantly reduced. The write to read switching circuit of the present invention eliminates the low pass filter which is connected to a transconductance circuit. Additionally, the present invention eliminates a switch in the Rmr measurement circuit and provides a switchless Rmr measurement circuit. Furthermore, the present invention provides a write to read switching circuit which only uses a internal ground as a reference. More specifically, the write to read switching circuit is directly connected to internal ground through a resistor which is connected to the reference voltage generator.
REFERENCES:
patent: 4644253 (1987-02-01), Libert
patent: 5204789 (1993-04-01), Jove et al.
patent: 5296975 (1994-03-01), Contreras et al.
patent: 5563501 (1996-10-01), Chan
Cho Hae-Seok
Ranmuthu Indumini
Brady W. James
Holder Regina N.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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