Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-07
2001-07-31
Malzahn, David H (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06269387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital computing, and more particularly to an apparatus and method for a three logic-level 32-bit adder/subtractor that implements carry-propagate logic.
2. Description of the Related Art
Traditional Binary Addition
In most computer systems, addition and subtraction of numbers is supported. In systems using traditional binary logic, the truth table for one-bit addition is set forth in Table 1.
TABLE 1
A
B
A + B
0
0
0
0
1
1
1
0
1
1
1
0*
In the last row of Table 1, a carry condition occurs. That is, the result is 0, but a carry into the next-higher-order bit position, corresponding to a decimal value of 2, has conceptually occurred.
In addition to single bits, the addition operation may be performed on multiple bits, including addition of two two-bit values. The truth table for such an operation is set forth in Table 2, where the first operand A is a two-bit value comprising bits A
0
and A
1
. The second operand, B, is a two-bit value comprising bits B
0
and B
1
.
TABLE 2
A =
B =
A + B =
Decimal
Decimal
Dec.
A
1
A
0
B
1
B
0
Value
Value
A + B
Value
0
0
0
0
0
0
00
0
0
0
0
1
0
1
01
1
0
0
1
0
0
2
10
2
0
0
1
1
0
3
11
3
0
1
0
0
1
0
01
1
0
1
0
1
1
1
10
2
0
1
1
0
1
2
11
3
0
1
1
1
1
3
00*
0
1
0
0
0
2
0
10
2
1
0
0
1
2
1
11
3
1
0
1
0
2
2
00*
0
1
0
1
1
2
3
01*
1
1
1
0
0
3
0
11
3
1
1
0
1
3
1
00*
0
1
1
1
0
3
2
01*
1
1
1
1
1
3
3
10*
2
Each output value in the “A+B” column of Table 2 indicated with an asterisk denotes a carry condition where a logical one has conceptually carried into the next-higher-order bit (the bit position corresponding to a decimal value of four).
N-nary Logic
The N-nary logic family supports a variety of signal encodings, including 1-of-4. The N-nary logic family is described in a copending patent application, U.S. patent application Ser. No. 09/019,355, filed Feb. 5, 1998, now U.S. Pat. No. 6,066,965, and titled “Method and Apparatus for a N-Nary logic Circuit Using 1-of-4 Encoding”, which is incorporated herein for all purposes and is hereinafter referred to as “The N-nary Patent.” In 1-of-4 encoding, four wires are used to indicate one of four possible values. In contrast, traditional static logic design uses two wires to indicate four values, as is demonstrated in Table 2. In Table 2, the A
0
and A
1
wires are used to indicate the four possible values for operand A: 00, 01, 10, and 11. The two B wires are similarly used to indicate the same four possible values for operand B. “Traditional” dual-rail dynamic logic also uses four wires to represent two bits, but the dual-rail scheme always requires two wires to be asserted. In contrast, N-nary logic only requires assertion of one wire. The benefits of N-nary logic over dual-rail dynamic logic, such as reduced power and reduced noise, should be apparent from a reading of The N-nary Patent.
All signals in N-nary logic, including 1-of-4, are of the 1-of-N form where N is any integer greater than one. A 1-of-4 signal requires four wires to encode four values (0-3 inclusive), or the equivalent of two bits of information. More than one wire will never be asserted for a 1-of-N signal. Similarly, N-nary logic requires that a high voltage be asserted for all values, even 0.
Any one N-nary gate may comprise multiple inputs and/or outputs. In such a case, a variety of different N-nary encodings may be employed. For instance, consider a gate that comprises two inputs and two outputs, where the inputs are a 1-of-4 signal and a 1-of-2 signal and the outputs comprise a 1-of-4 signal and a 1-of-3 signal. Various variables, including P, Q, R, and S, may be used to describe the encoding for these inputs and outputs. One may say that one input comprises 1-of-P encoding and the other comprises 1-of-Q encoding, wherein P equals two and Q equals four. Similarly, the variables R and S may be used to describe the outputs. One might say that one output comprises 1-of-R encoding and the other output comprises 1-of-S encoding, wherein R equals four and S equals 3. Through the use of these, and other, additional variables, it is possible to describe multiple N-nary signals that comprise a variety of different encodings.
SUMMARY OF THE INVENTION
The present invention is an apparatus that takes two N-nary operands and performs an arithmentic operation, either addition or subtraction, on them to produce a result. In the preferred embodiment, the operands comprises two 32-bit 1-of-4 operands. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands. The HPG signals are used to create “block” HPG indicators for blocks of dits. A 1-of-2 ADD/SUB selector signal may be used to select whether addition or subtraction is performed. In subtraction for two 1-of-4 operands, subtraction is implemented as three's complement addition. In the least significant dit, the three's complement of the A operand is incremented by one, to create the four's complement, before it is added to the B operand. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit. The present invention produces as outputs a 32-bit 1-of-4 sum and a 1-of-2 carry signal.
REFERENCES:
patent: 3987291 (1976-10-01), Gooding et al.
patent: 5299145 (1994-03-01), Yoshida
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5463573 (1995-10-01), Yoshida
patent: 5467298 (1995-11-01), Yoshida
patent: 5600583 (1997-02-01), Bosshart et al.
patent: 5943251 (1999-08-01), Jiang et al.
Blomgren James S.
Petro Anthony M.
Booth Matthew J.
Booth & Wright, L.L.P.
Intrinsity, Inc.
Malzahn David H
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