Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-01-22
2003-07-22
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S376000, C370S379000
Reexamination Certificate
active
06597690
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data transfer in a time division multiplexing environment. More particularly, the present invention relates to using associative memories to implement a limited switching scheme that transfers data in a time division multiplexing environment.
BACKGROUND
Improvements in communications networks have led to robust designs that support multiple devices connected to a single bus. Typically the supported devices consist of microprocessors, memory devices, digital to analog converters, analog to digital converters, digital signal processing devices, printers, modems, and universal serial bus hubs. The communication between the multiple devices is governed by the type of network and the band width of the individual devices. A conventional communication scheme that reduces connection costs while increasing portability between devices is a shared serial interface.
In a shared serial interface, each device coupled to the shared interface transmits/receives data on the shared serial bus. Typically, the shared serial bus includes a data line, a clock, and control signals. In the prior art, a full-switch in conjunction with a time division multiplexing (“TDM”) scheme is used to schedule the transmission of data across the shared serial bus. TDM is the division of a time interval, also denoted as a frame, into a number of equal sub-intervals called time slots. The beginning of each time frame is typically identified by a start of frame (“SOF”) signal transmitted along the shared serial bus. The TDM scheme allocates one or more time slots to each device coupled to the shared serial bus. Accordingly, the device can only transmit/receive data on an assigned time slot(s). The allocation of time slots and transmit commands is maintained by the full-switch.
FIG. 1
illustrates a prior art full-switch TDM system. In particular, system
100
includes input
110
, memory devices (RAM
120
and
150
), output
130
, and control
140
. Input
110
transfers the serial data from each transmitting device—typically referred to as an incoming TDM stream—to system
100
. Output
130
transmits serial data from system
100
—typically referred to as an outgoing TDM stream—to each receiving device.
Control
140
switches the data stream on input
110
to create a different output stream on output
130
, thus creating a switching mechanism between different devices coupled to input
110
and output
130
. Specifically, control
140
sequentially writes data for each time slot into an address of RAM
120
. For example, data received in the first time slot is written into the first address of RAM
120
and data received in the second time slot is written into the second address of RAM
120
. As previously described, each time slot corresponds to a different device transmitting data. Thus, in the present example, device one writes data to the first memory address of RAM
120
and device two writes data to the second memory address of RAM
120
. After writing the input data stream to RAM
120
, control
140
uses memory
150
to generate an output data stream.
As illustrated in
FIG. 1
, control
140
is also connected to memory
150
. Each address of memory
150
corresponds to a specific time slot on the outgoing stream
130
. Each address of memory
150
also contains connection information that determines which address of RAM
120
should be transmitted on output
130
. For example, the third memory address of memory
150
stores data having a value of ‘thirty-two.’ Accordingly, during time slot
3
, the data stored in the thirty-second memory address of RAM
120
, from a previous time frame, is transmitted on output
130
. Thus, resulting in the transfer of data from the device transmitting on slot thirty-two to a specific device that receives data in the third time slot. The specific device that receives data during the third time slot is pre-determined by system
100
.
A full-switch TDM system provides a data transfer mechanism that switches data between all time slots in any given order. Thus, the full-switch TDM system allows any two devices coupled to the shared serial line to transfer data. The full-switch TDM system, however, results in numerous disadvantages.
One disadvantage of using a full-switch TDM system results from the size requirements of RAM
120
and memory
150
. In a thirty-two time slot TDM scheme, both RAM
120
and memory
150
require thirty-two rows of memory cells. The large memory requirements result in system
100
using a significant area. The large memory requirements also result in an increased cost for system
100
.
Another disadvantage of using a full-switch TDM system results from a network system where all the time slots in the TDM scheme are not required. For example, in a thirty-two time slot TDM scheme used in a system with only four devices only the first four memory addresses of RAM
120
and memory
150
are used during data transfer. In this network environment, memory locations five through thirty-two of RAM
120
and memory
150
remain unused.
SUMMARY OF THE INVENTION
A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.
REFERENCES:
patent: 3599160 (1971-08-01), Neptune et al.
patent: 4071703 (1978-01-01), Schaffter
patent: 4093827 (1978-06-01), Charransol et al.
patent: 4370742 (1983-01-01), Minamitani et al.
patent: 4392221 (1983-07-01), Hesketh
patent: 4450557 (1984-05-01), Munter
patent: 4470139 (1984-09-01), Munter
patent: 4510597 (1985-04-01), Lewis
patent: 4616360 (1986-10-01), Lewis
patent: 4638474 (1987-01-01), Chalet
patent: 4639910 (1987-01-01), Toegel et al.
patent: 4656626 (1987-04-01), Yudichak et al.
patent: 4759010 (1988-07-01), Murata et al.
patent: 4759012 (1988-07-01), Suzuki
patent: 4905226 (1990-02-01), Kobayashi
patent: 4918597 (1990-04-01), Krishnan et al.
patent: 4922416 (1990-05-01), Krishnan et al.
patent: 5031094 (1991-07-01), Toegel et al.
patent: 5060227 (1991-10-01), Finley et al.
patent: 5381406 (1995-01-01), Yamashita
patent: 5422838 (1995-06-01), Lin
patent: 5515428 (1996-05-01), Sestak et al.
patent: 5539816 (1996-07-01), Pinard et al.
patent: 5790545 (1998-08-01), Holt et al.
patent: 6034965 (2000-03-01), Pollack et al.
patent: 6067296 (2000-05-01), Heering et al.
patent: 6070223 (2000-05-01), Yoshizawa et al.
Mehta Kalpesh D.
Shetty Krishna
Blakely , Sokoloff, Taylor & Zafman LLP
Hsu Alpus H.
LandOfFree
Method and apparatus employing associative memories to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus employing associative memories to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus employing associative memories to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3019119