Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
1997-12-31
2001-08-21
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S208000
Reexamination Certificate
active
06279102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method and an apparatus useful in processors and computers, and more particularly, to a method and apparatus for employing a combined rename table for more than one class of register.
2. Description of the Related Art
Many processors and similar hardware structures increase instruction throughput by executing instructions either in parallel or out-of-order. An out-of-order processor is ordinarily more efficient when the execution order is more flexible. The small number of registers in many modern computers introduces artificial dependencies among instructions that lower the flexibility of the execution order. Renaming of registers eliminates some of the artificial dependencies that reduce the efficiency of out-of-order execution.
Decoding expands macro-instructions into simpler instructions referred to as micro-operations (micro-ops). Decoding introduces “temporary” registers as source or destination addresses of the micro-ops for storing intermediate results. When the same temporary register appears in more than one micro-op, a dependency occurs. Dependencies occurring in write-after-write and write-after-read sequences of micro-ops are artificial and can be removed by the renaming of registers.
FIG. 1
illustrates the effect of renaming on the execution of a write-after-write sequence of micro-ops, i.e. two micro-ops having the same register as a destination address. At block
1
, micro-ops
2
,
3
,
4
are in the original instruction order. A register T is the destination address of the first and second micro-ops
2
,
3
and is a source address of the third micro-op
4
. Thus, the execution of the third micro-op
4
uses data stored in the register T by the second micro-op
3
. If execution order of the first and second micro-ops
2
,
3
is inverted, the execution of the third micro-op
4
uses data stored in the register T by the first micro-op
2
instead of data stored in the register T by the second micro-op
3
. Therefore, inverting the execution order of two micro-ops with the same destination register changes the results coming from the execution of later microops that use the results from executing one of the earlier micro-ops.
Renaming has replaced each occurrence of a register as a destination address by a different physical register. For example, renaming replaces the destination register T of the first and second micro-ops
2
,
3
, of block
1
, by the physical registers R and R′ to produce renamed micro-ops
5
,
6
of block
7
having different destination registers. Renaming also consistently replaces registers in the source addresses of dependent micro-ops by physical registers. For example, the source register T of the third micro-op
4
of block
1
is replaced by R′ to give a third micro-op
8
of block
7
. After renaming, the destination register R of the first micro-op
5
is not an address of the third micro-op
8
. Subsequent to renaming, the first and renamed second micro-ops
5
,
6
may be executed in-order or in reverse-order without changing the results coming from the dependent third micro-op
8
.
FIG. 2
illustrates a portion of a prior art out-of-order processor
14
. The processor
14
has a rename table
15
for integer registers (not shown) and a rename table
16
for floating-point registers (not shown). Data words from an integer and a floating-point register have different interpretations, e.g., different bits represent the exponents, and are often used by different execution hardware. Rows
17
,
18
,
19
,
21
,
22
,
23
of the rename tables
15
,
16
are indexed by the respective integer and floating-point temporary registers used by the decoder
24
. Entries on each row
17
,
18
,
19
,
21
,
22
,
23
are the names of physical integer and floating-point registers replacing the temporary registers assigned by the decoder
24
. A rename unit
25
replaces each temporary register appearing as a destination address with a physical integer or floating-point register.
The rename unit
25
is contains the rename tables
15
,
16
. The rename unit
25
writes the identity of physical registers as entries in the rows
17
,
18
,
19
,
21
,
22
,
23
of the corresponding temporary registers in the appropriate rename table
15
,
16
. The rename unit
25
also looks up temporary registers appearing as source addresses of micro-ops in the rename tables
15
,
16
. The rename unit
25
replaces these source temporary registers by the corresponding of physical registers.
Modem trends in processor design involve increasing operating frequencies. Higher frequencies often demand simpler micro-ops that are executable in shorter times. Decoding macro-instructions into the simpler micro-ops generally requires more temporary registers to store more intermediate results. Furthermore, processors using simpler micro-ops rely on more nested routines to deal with special situations that cannot be handled by the simpler micro-ops. The nested routines use temporary registers to store previous results while performing the routine. In both cases, the simpler micro-ops of future higher frequency processors will ordinarily have need for temporary registers assigned by the decoders. One way to accommodate more temporary registers is to increase the size of the rename table. But, the rename table already occupies a substantial amount of precious space on the chip die. Increasing the size may be prohibited by contemporary manufacturing limits on die sizes. Furthermore, the size of the rename unit would increase if the size of the rename table was increased. The size increase to the rename unit could lower the frequency at which renaming could be performed.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect the present invention provides for an apparatus that includes at least two physical registers and a rename unit to assign at least one of the physical registers to an original register. The original register appears as a destination address in a micro-op. The apparatus includes a rename table having a location for recording the assigned physical register to the original register. The location has at least one bit for indicating whether the assigned physical register belongs to a first or a second class. The rename table is connected to the rename unit and is adapted to lookups of the assigned physical register.
REFERENCES:
patent: 5627985 (1997-05-01), Fetterman et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5876016 (1999-10-01), Eisen et al.
patent: 5890008 (1999-03-01), Panwar et al.
patent: 6081880 (2000-06-01), Sollars
Blakely , Sokoloff, Taylor & Zafman LLP
Eng David Y.
Intel Corporation
LandOfFree
Method and apparatus employing a single table for renaming... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus employing a single table for renaming..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus employing a single table for renaming... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2504966