Method and apparatus compensating for frequency drift in a...

Details Method and apparatus compensating for frequency drift in a... Method and apparatus compensating for frequency drift in a...

2006-05-16

2006-05-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S161000

Reexamination Certificate

active

07046060

ABSTRACT:
A delay locked loop (DLL) according to the present invention includes a cycle time detector to determine the quantity of delay elements within a clock cycle and adjust a DLL counter controlling a DLL variable delay line to enable operation or locking in response to DLL overflow and underflow conditions. The cycle time detector includes a ring oscillator having a strong correlation between the oscillator period and the DLL delay elements. The output of the oscillator controls the counter to provide a new locking position for the DLL in the presence of overflow or underflow conditions. The oscillator is driven for an interval corresponding to the product of the external clock period and the quantity of delay elements in the ring oscillator. In effect, the delay of the DLL is adjusted to the preceding or succeeding external clock period to enable locking in response to overflow or underflow conditions.

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Kirk, B.; “Clock Management with PLLs and DLLs”; retrieved from Internet; Mar. 28, 2001; http://www.eedesign.com/article/showArticle.jhml?articleld=16502784; 7 pages.

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