Patent
1995-01-09
1996-10-08
Harvey, Jack B.
395280, 395290, G06F 1300
Patent
active
055641148
ABSTRACT:
A computer system is provided with a central processing unit (CPU), a bus master coupled to the CPU, and a plurality of interface cards that interface the computer system with peripheral devices. A plurality of host adapters are coupled between the bus master and the interface cards. The host adapters adapt signals between the CPU and the interface cards. Each host adapter generates a ready signal that when asserted indicates readiness of the host adapter to receive address information from the bus master and have data information read by the bus master. An address/data bus is coupled between the bus master and the host adapters. A single separate ready line is coupled between each of the host adapters and the bus master, each ready line carrying the ready signal from a different one of the host adapters to the bus master. The single ready signal carried by a single line serves both an address ready and a data ready signalling function, to thereby, reduce the pin count in the host adapter serving as a slave.
REFERENCES:
patent: 4162541 (1979-07-01), Hartke
patent: 4785394 (1988-11-01), Fischer
patent: 5436621 (1995-07-01), Macko et al.
patent: 5448703 (1995-09-01), Amini et al.
Popat Kaushik L.
Sugie Fukuji
Cirrus Logic Inc.
Harvey Jack B.
Travis John
LandOfFree
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