Method and a system for fixing hold time violations in hierarchi

Details Method and a system for fixing hold time violations in hierarchi Method and a system for fixing hold time violations in hierarchi

1995-10-13

1999-04-20

Butler, Dennis M.

Boots, shoes, and leggings

364491, 395558, G06F 1500

Patent

active

058962999

ABSTRACT:
The invention relates to a computer implemented process for fixing hold time violations in hierarchical designs of electronic circuits. The process comprises the steps of:

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patent: 5774371 (1998-06-01), Kawakami
K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching", 24th Design Automation Conference, pp. 341-346 (1987).
A. Ginetti et al (Aramis, Belgium), "Using the Asic Synthesizer in DSP Designs", DSP, The Enabling Technology For Communications, Mar. 9-10, 1993, Amsterdam.
D. Brasen et al, "Post-Placement Technology Mapping", VLSI 93, Sep. 6-10, 1993, Grenoble.

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