Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2000-09-01
2001-12-04
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S035000
Reexamination Certificate
active
06326827
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to clock signal distribution techniques, and, in particular, to a method and circuit for regulating the duty cycle of a clock signal.
BACKGROUND OF THE INVENTION
The duty cycle of a clock signal is subjected to distortions because of asymmetries along the clock distribution tree due to load mismatches, different threshold levels, changes of logic levels (e.g., CMOS), variations of the power supply, noise, etc.
When the clock frequency approaches the maximum allowed for the technology used, problems arise in controlling the duty cycle along the clock distribution tree. On the contrary, when the clock frequency is relatively low, it becomes relatively easy to ensure good control of the duty cycle by an appropriate design. This design is dependent upon the availability of a good model of the clock tree. Poor model and/or poor design tools may lead to problems.
Duty cycle degradation is due to the use of standard buffers for distributing the clock. This is because standard buffers are usually designed for minimizing power consumption and delay figures and equalizing rise/fall delays and slopes. Duty cycle integrity is often regarded as a less important aspect when designing standard libraries.
This problem is well known and there have been several approaches for overcoming it. A significant bibliography may include the following titles:
1) EP No. 0892497-A1 titled “Procede De Multiplication De La Frequence D'un Signal D'horloge Avec Controle Du Rapport Cyclique, Et Dispositif Correspondant” (X. Cauchy—STMicroelectronics);
2) WO 97/42707, titled “Clock Signal Generator” (U. Grehl—Siemens);
3) EP No. 0930709, titled “Circuit For Producing Pulse Signal With A Desired Duty Cycle” (Y. Hiroshi—NEC);
4) U.S. Pat. No. 5,757,218, titled “Clock Signal Duty Cycle Correction Circuit And Method” (D. W. Blum—IBM);
5) U.S. Pat. No. 5,841,305, titled “Circuit And Method For Adjusting Duty Cycles” (J. E. Wilson—Cypress);
6) EP No. 0905896, titled “Output Buffer Circuit With 50% Duty Cycle” (W. Hiroyuki—NEC);
7) U.S. Pat. No. 5,856,753, titled “Output Circuit For 3V/5V Clock Chip Duty Cycle Adjustment” (P. Xu—Cypress);
8) U.S. Pat. No. 5,812,832, titled “Digital Clock Waveform Generator And Method For Generating A Clock Signal” (S. C. Horne—AMD);
9) U.S. Pat. No. 5,828,250, titled “Differential Delay Line Clock Generator With Feedback Phase Control” (K. Konno—Intel);
10) U.S. Pat. No. 5,410,263, titled “Delay Line Loop For On-chip Clock Synthesis With Zero Skew And 50% Duty Cycle” (A. Waizman—Intel);
11) U.S. Pat. No. 5,491,440, titled “Automatic Clock Duty Cycle Adjusting Circuit” (T. Uehara—Ando Electric);
12) IEEE-JSSCC, Vol. 29, No. 12, December 1994, titled “A 2.5 V CMOS DLL For An 18 Mbit, 500 Mbyte/s DRAM” (T. H. Lee et al.);
13) EP No. 98830542.1, titled “A Fully Digital Phase Aligner” (F. Cretti, N. Villa—STMicroelectronics).
The duty cycle can be controlled and adjusted by delaying each clock edge using a tapped delay line as disclosed in 1) EP No. 0892497-A1, 2) WO 97/42707, and 3) EP No. 0930709. This is not suitable at relatively high frequencies because of an excessive coarseness in the corrections.
The low speed approach disclosed in 4) U.S. Pat. No. 5,757,218 is good for portability, controllability and easy to use, but is not suited for high frequency applications because it requires a clock running much faster than the clock to be controlled.
The techniques disclosed in 5) U.S. Pat. No. 5,841,305, 6) EP No. 0905896, and 7) U.S. Pat. No. 5,856,753 are applicable to an I/O buffer pre-driver, when the signal being controlled must be adapted to a different logic level (e.g., CMOS, TTL) or to a different power supply level (2.5, 3, 5 V). These techniques are not based on feedback, and, therefore, are applicable when the adjustment is a known design constraint.
Rather complex methods for producing a clock having a controlled frequency, duty cycle and skew are disclosed in 8) U.S. Pat. No. 5,812,832, 9) U.S. Pat. No. 5,828,250, and 10) U.S. Pat. No. 5,410,263. These methods are suitable for managing clock distribution in large devices such as microprocessors, but are not easily embedded nor portable and require a rather complex design.
Several analog approaches are available, including stand alone as disclosed in 11) U.S. Pat. No. 5,491,440, or included in DLL/PLL circuits as disclosed in 12) IEEE-JSSCC, Vol. 29, No. 12, December 1994. An analog approach cannot be easily implemented in a digital environment because an analog design, while solving the adjustment of a clock, puts tight constraints on the environment (the chip) where the analog circuits are embedded. The analog approach may operate in an isolated environment but becomes prone to operating failures when neighboring digital circuits cause a disturbance. This disturbance is inevitable because of the injection of noise on sensitive parts of the analog circuit.
A rule of thumb when handling analog parts is to keep the parts isolated as much as possible from the most noisy parts of the digital sectors. This problem becomes quite serious when analog parts are co-integrated on a digital chip. It is difficult to ensure a complete isolation between the analog part and the noisy digital parts.
Existing digital approaches are not suitable for very high speed applications because both require clocks having significantly higher speed or are very complex, and, therefore, require an excessively large area of integration.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is an object of the present invention to provide a method for regulating the duty cycle of a clock signal, and to provide a digital implementing circuit for doing so. The method and digital implementing circuit are relatively straightforward to implement, reliable and readily integrable. The circuit of the invention will often be referred to by the acronym DCA in the following description, which means Duty Cycle Adjuster.
This and other objects, advantages and features in accordance with the present invention is provided by a method for the closed-loop regulation of the duty cycle of an input clock signal. The method includes producing a second clock signal by a first controlled delay circuit varying the duty cycle, and providing the second clock signal to a first circuitry and to a second circuitry for respectively increasing and decreasing the duty cycle of the second clock signal.
The method further includes monitoring which of the first circuitry incrementing the duty cycle and of the second circuitry reducing the duty cycle saturates first, and regulating the delay introduced by the first controlled delay circuit until the saturation intervals of the first circuitry and of the second circuitry equal each other.
The closed-loop clock duty cycle regulating circuit of the invention comprises a controlled delay line varying the duty cycle of an input clock signal and outputting a second clock signal. A first and a second circuitry respectively increases and decreases the duty cycle of the second clock signal. The regulating circuit further includes a third circuitry producing a signal indicating which of the first and second circuits saturates first, and a fourth circuitry controlling the delay line for increasing the duty cycle of the second clock signal. The duty cycle is increased if the third circuitry detects first the saturation of the second circuitry. The duty cycle is decreased if the third circuitry detects first the saturation of the first circuitry.
The invention is effective because it optimally meets numerous important conditions or requirements, such as:
1) extension of the frequency range is no longer required because the need of a DCA (Duty Cycle Adjuster) arises only at frequencies close to the technological limit;
2) duty cycle measurement is carried out in a straightforward and precise manner without using methods based on comparisons among replicas or on the synthesis of pulses of established duration, etc.;
3) a good adjustment precision is not required, considering that in
Cretti Francesco
Izzo Raffaele
Villa Nuccio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Callahan Timothy P.
Galanthay Theodore E.
Nguyen Linh
STMicroelectronics S.r.l.
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