Method and a jitter buffer regulating circuit for regulating...

Details Method and a jitter buffer regulating circuit for regulating... Method and a jitter buffer regulating circuit for regulating...

2004-03-12

2009-06-30

Mattis, Jason E (Department: 2416)

Multiplex communications

Data flow congestion prevention or control

Flow control of data transmission through a network

C370S230100, C370S412000

Reexamination Certificate

active

07554915

ABSTRACT:
Transmission delays due to the buffering of data packets are registered for the purpose of regulating a jitter buffer. Weighted mean delay values are continuously derived from registered transmission delays, with a shorter transmission delay receiving a higher weighting than a longer transmission delay. A read-out speed of the jitter buffer is then regulated as a function of the continuously derived weighted mean delay values in such a way that the weighted mean delay values are adjusted as a regulating variable to a predefined desired delay.

REFERENCES:
patent: 6366959 (2002-04-01), Sidhu et al.
patent: 6434606 (2002-08-01), Borella et al.
patent: 6512761 (2003-01-01), Schuster et al.
patent: 6820128 (2004-11-01), Firoiu et al.
patent: 2003/0112758 (2003-06-01), Pang et al.
patent: WO 95/14337 (1995-05-01), None
patent: WO 01/93516 (2001-12-01), None

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