Method and a device for synchronizing a signal

Details Method and a device for synchronizing a signal Method and a device for synchronizing a signal

1992-07-29

1994-06-07

Chin, Stephen

Pulse or digital communications

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331 25, 328 72, 375120, H03D 324

Patent

active

053196813

ABSTRACT:
A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator. The device also includes circuitry for decrementing the first number when the latest stored logic states of the phase comparator have a single occurrence of the first logic state and for incrementing the second number when the latest stored logic states of the phase comparator have a single occurrence of the second state.

REFERENCES:
patent: 4715050 (1987-12-01), Tanaka et al.
patent: 4748644 (1988-05-01), Silver et al.
patent: 4841167 (1989-06-01), Sargusa
patent: 4870684 (1989-09-01), Arai et al.
patent: 4890305 (1989-12-01), Devries
patent: 5077529 (1991-12-01), Ghoshal et al.
John Snyder "Digital Phase-Locked Loop Finds Clock Signal in Bit Stream", Electronics Aug. 30, 1979 vol. 52, No. 18.

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