Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-07-18
2003-02-11
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06519183
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to non-volatile semiconductor memories and, more particularly, to a method and to a circuit structure for modifying the threshold voltages of the cells of a memory.
BACKGROUND OF THE INVENTION
A typical EEPROM memory is formed on a substrate of semiconductor material as a matrix of memory cells, each constituted by a body region with p-type conductivity in which two (source and drain) regions with n-type conductivity are formed, separated by a channel region. A floating-gate electrode is disposed above the channel region and is insulated therefrom by a thin layer of dielectric material. A control gate electrode extends above the floating gate electrode and is insulated therefrom by another layer of dielectric material.
The cells of the matrix have their source regions connected together to a common terminal which, during programming and reading, is generally connected to the negative (ground) terminal of the supply of the integrated circuit of which the memory forms part. The drain regions of the cells of each column of the matrix are connected to one another by common connection lines, known as bit lines or column lines. The control gate electrodes of the cells of each line are connected to one another by common connection lines known as word lines or row lines. A memory structure of this type is known as a NOR-matrix memory.
Each cell of the matrix can be selected by a row decoder and a column decoder. Once selected, the cell can be polarized by the application of suitable potentials to its terminals and its state can be investigated by means of a sense amplifier connected in series with the respective bit line.
In order to write or program a cell of the memory, the bit line and the word line which identify it are brought to predetermined potentials higher than the common source potential, for example 5V and 9V, respectively, such as to bring about a flow of “hot electrons” through the thin dielectric layer from the substrate to the floating-gate electrode. The electrons which accumulate in the floating-gate electrode bring about an increase (of 2-4V) in the threshold voltage of the cell.
In order to read a cell, the common source terminal is connected to ground, the bit line (drain) is brought to a positive potential, the word line (control gate) is brought to a positive potential higher than that of the bit line, and the drain current is measured by the sense amplifier. A non-programmed cell (logic level “1”) conducts a relatively high current (for example 50 &mgr;A) whereas a programmed cell (logic level “0”) conducts a considerably lower current.
In order to erase a cell, a positive potential (for example, 5V) is applied to the common source terminal, a negative potential (for example, −8V) is applied to the word line (control gate), and the bit line (drain) is left floating. In these conditions, a strong electric field is developed between the floating-gate electrode and the source region so that the negative charge formed by the accumulated electrons is extracted from the floating-gate electrode by the tunnel effect. In a flash EEPROM memory, erasure takes place simultaneously for all of the cells of the matrix or for the cells of a selected section of the matrix.
More particularly, in order to perform the erasure, a series of voltage pulses is applied to the cells so as to extract electrons from the floating gate by the tunnel effect. An operation is generally performed after each pulse to check the state of each individual cell in order to see whether it has reached the “1” state, that is, the erased cell state. In practice, the cell is biased for reading and its drain current is measured. If the current measured is below a predetermined value, which indicates that the conduction threshold has not been reached, a further erasure pulse is applied. These operations are repeated until the cell with the highest threshold within the matrix is recognized as an erased cell.
Since the operation to erase a flash EEPROM memory is not selective, the cells which have already been recognized as erased continue to be subjected to erasure pulses. Since each erasure pulse involves the removal of electrons from the floating gate, the thresholds of these cells will continue to be lowered upon each pulse. When all of the cells have been recognized as erased, some of them will therefore have very low or even negative threshold voltages, and will thus behave as depletion transistors. A typical distribution of threshold voltages Vth of the cells after erasure is shown in
FIG. 1
in which D.V. and E.V. indicate two predetermined voltage values, as will be explained below, and Log # indicates the logarithm of the number of cells of the memory or of the section in question.
Cells with thresholds below a certain value are the cause of potential reading errors. In fact, it should be borne in mind that, in order to read a cell, positive voltages are applied both to the column and to the row which contain the cell, and the remaining rows are connected to ground. If the column line selected contains a cell which has been erased excessively until it has a threshold below zero, when the respective row line is grounded, the cell will have its gate electrode at zero and will therefore be conductive, thus potentially causing a false reading.
The excessively erased cells also cause leakage currents during programming. In fact, for programming, positive voltages are also applied to a selected column and a selected row whilst the non-selected rows are connected to ground. An excessively erased cell in the selected column is also conductive when the respective row is not selected so that, in the selected column, there will therefore be a spurious current which may overload the supply of the column lines.
To prevent the problems described above, the threshold of each erased cell must be below a maximum value generally known as the erase verify point, indicated E.V. in
FIG. 1
, but above a minimum value, generally referred to as the depletion verify point, indicated D.V. in FIG.
1
. In other words, the condition that the threshold values of the erased cells of the memory should all be within a “range” of values delimited by the two verify points must be satisfied.
With the tendency to design integrated circuits, and particularly memories, with ever lower supply voltages, the erase verify point falls to very low values. Moreover, since the precise breadth of the distribution of the threshold values of the cells upon completion of the erasure operation is difficult to predict and may in any case undergo variations during the life of the device (because of the variability of the parameters of the manufacturing process, of the erasure method selected, of the ageing state, that is, of the number of programming-erasure cycles to which the memory has been subjected, and of occasional anomalies in the conduction characteristics of the tunnel dielectrics), the condition indicated above is ever more difficult to satisfy.
In order to bring the thresholds of the erased cells within the “range” of values delimited by the two verify points, a known method provides for “soft” programming operations after the erasure of the cells. In practice, the cells whose thresholds are below the depletion verify point are identified and are subjected to a programming operation, for example, by the application of voltage pulses of increasing amplitude to their gate electrodes, followed by a verification operation each time, until a threshold above the depletion verify point is recognized. Upon completion of the “soft” programming operations, the distribution of threshold voltages should be as shown in FIG.
2
.
The soft programming is performed automatically after an erasure operation by suitable control circuits. To ensure a high level of reliability of the devices, these circuits have to be designed so as to take into account process variability, the conditions of use of the device, and its ageing, so that the initial voltage selected for the corrective programming pu
Iannucci Robert
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tran M.
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