Metastable tolerant asynchronous interface

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328 74, 307269, 307271, 307475, 375108, 3642391, H03K 1716, H03K 5156

Patent

active

050458019

ABSTRACT:
The interface circuit passes data from a first unit running at one clock rate to a second unit running at another clock rate. READY leads from an In control circuuit to an Out control circuit are used to signal when a data word has been loaded by the first unit; and TAKEN leads from the Out control circuit to the In control circuit are used to signal when a data word has been received by the second unit. An anti-Metastable Flip-flop (AMF) is used with each READY lead and each TAKEN lead. Each AMF flip-flop comprises an input latch, an output latch, a decentration driver, and an oscillation suppressor. The decentration driver handles cases in which the output of the input latch is balanced and floating or balanced and driven by tugging the output of the input latch toward a logic 0 soon after an active edge of a signal on the flip-flop clock lead has caused the input latch to close. The oscillation suppressor is coupled between the input latch and the output latch for eliminating oscillation by delaying output signals from the input latch by various times and anding the differently delayed signals together. Thus the interface circuit supresses the effects of metastable states by forcing the flip-flop output to a reliable logic 0 or 1 when it is in a metastable state. The circuit disclosed herein is unique in that it suppresses states in asynchronous interfaces without inserting additional flip-flop delays, or requiring retransmission of data.

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