Metastable resistant flip-flop

Details Metastable resistant flip-flop Metastable resistant flip-flop

1987-09-17

1990-05-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307291, 307269, 307480, 328 63, 328 34, H03K 3284, H03K 1716

Patent

active

049298500

ABSTRACT:
A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.

REFERENCES:
patent: 3947697 (1976-03-01), Archer et al.
patent: 4498176 (1985-02-01), Wagner
patent: 4575644 (1986-03-01), Leslie
patent: 4745302 (1988-05-01), Hanawa et al.

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