Metastable-proof flip-flop

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 3072722, H03K 3356, H03K 19003

Patent

active

049995286

ABSTRACT:
A clocked electronic flip-flop device which uses a novel method of storing digital data that is immune to metastability, regardless of data input level or timing, is disclosed. The method includes first converting the data input level to a stored voltage level which, in turn, is operably disconnected from its input source after the active transition of an external clock signal. In a preferred embodiment, the data input level is combined in an EXCLUSIVE OR circuit with the existing state of the flip-flop device to produce the stored voltage. The stored voltage is processed by a high-speed comparator which causes an internal clock pulse to be generated if and only if the amplitude of the stored voltage level exceeds a predetermined threshold level range. The internal clock pulse, if generated, is then used to toggle a conventional type flip-flop element comprising the output stage of the device into the opposite logic state. If the stored voltage level is too small to cause an internal clock pulse to be generated, it indicates that the data input signal level was not at the logic state which required a change of state. In either instance, the resultant state of the flip-flop device according to this invention is always proper for the given data input level and timing with respect to the active transition of the external clock input.

REFERENCES:
patent: 4544850 (1985-10-01), Tarleton
patent: 4642484 (1987-02-01), Skovmand et al.
patent: 4686391 (1987-08-01), Gudaitis
patent: 4689497 (1987-08-01), Umeki et al.
patent: 4820939 (1989-04-01), Sowell et al.
patent: 4929850 (1990-05-01), Breuninger

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