Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-05-26
2001-05-01
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S096000, C341S097000, C341S164000, C341S165000, C341S118000, C341S155000, C341S145000
Reexamination Certificate
active
06225937
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to analog-to-digital converters and more particularly to multiple analog-to-digital converters integrated on a monolithic integrated circuit.
2. Discussion of the Related Art
In conventional single slope methods of analog-to-digital conversion, a clocked comparator is employed to compare a sampled and held signal with an analog ramp. The clocked comparator in turn generates a signal that is used to clock a latch circuit that stores the state of a digital counter when the sampled and held signal is equal to the analog ramp. The stored counter value is a digital representation of the magnitude of the analog signal. Integrated circuit applications of this type of circuit provide an array of such circuits.
Conventional single slope analog-to-digital converters encounter resolution and speed limitations due to limitations on maximum clock rate. One limit to the maximum clock rate with the convention single slope converter is due to metastability. Metastability is defined as the instability of a flip-flop when the clock and data inputs change simultaneously. Although the output of a flip-flop cannot, in principle, be guaranteed to have settled to a valid logic state after any given period of time, the probability that the output has not settled decreases exponentially with time. After about 69 time constants, for example, the probability of the output not settling is less than 10
−30
, which is acceptable for most applications.
Due to this problem, the clock rate must be reduced substantially to allow the flip-flop, which synchronizes the comparator output to the system clock time, to recover from metastability. Conventional devices require the metastability resolution to be done at a frequency determined by the time resolution of the conversion. As a result, conventional devices are limited to clock rates much less than their circuits are capable of.
The invention improves on conventional devices by removing the requirement to synchronize individual converters to the master clock and by generating a higher resolution digital code. It is therefore one object of the invention to provide an analog-to-digital converter that realizes a significant improvement in resolution and speed compared to conventional converters.
SUMMARY OF THE INVENTION
The invention provides an apparatus to convert an analog signal to a digital signal comprising: an analog ramp generator having an analog ramp output, a digital ramp generator having a Gray coded digital ramp output, a comparator for comparing the analog signal with the analog ramp signal, wherein the comparator has a comparison output, and a metastability resolving latch for storing data having a first data input connected to the digital ramp output and an enable input connected to the comparison output, wherein the metastability resolving latch has a metastability resolved digital signal output.
The invention also provides an apparatus to convert a plurality of analog signals to a plurality of digital signals comprising: an analog ramp generator having an analog ramp output, a digital ramp generator having a Gray coded digital ramp output, a plurality of comparators for comparing the analog signal with the plurality of analog ramp signals, wherein the plurality of comparators has a plurality of comparison outputs, and a plurality of metastability resolving latches for storing data having a plurality of first data inputs connected to the digital ramp output and a plurality of enable inputs connected to the comparison output, wherein the plurality of metastability resolving latches have a plurality of metastability resolved digital signal outputs.
The invention also provides an analog-to-digital conversion method comprising the steps of operating an unclocked comparator to compare an input analog voltage to a voltage ramp to enable a digital latch to store a Gray coded digital timer word when the two comparator inputs are substantially equal.
The features and advantages of the present invention will be more readily understood and the apparent from the following detailed description of the invention, which should be read in conjunction with the accompanying figures, and from the claims which are appended at the end of the detailed description.
REFERENCES:
patent: 3393298 (1968-07-01), Olson
patent: 3891843 (1975-06-01), Parkin
patent: 3961325 (1976-06-01), Kendall et al.
patent: 3971015 (1976-07-01), Hornak
patent: 4151516 (1979-04-01), O'Neill
patent: 4176398 (1979-11-01), Rider
patent: 4298887 (1981-11-01), Rode
patent: 4369463 (1983-01-01), Anastassiou et al.
patent: 4513390 (1985-04-01), Walter et al.
patent: 4654622 (1987-03-01), Foss et al.
patent: 4752694 (1988-06-01), Hegel, Jr. et al.
patent: 5012246 (1991-04-01), Chung et al.
patent: 5045685 (1991-09-01), Wall
patent: 5045854 (1991-09-01), Windmiller
patent: 5050065 (1991-09-01), Dartois et al.
patent: 5084704 (1992-01-01), Parrish
patent: 5084841 (1992-01-01), Williams et al.
patent: 5132685 (1992-07-01), DeWitt et al.
patent: 5200623 (1993-04-01), Cannata
patent: 5204761 (1993-04-01), Gusmano
patent: 5268576 (1993-12-01), Dudley
patent: 5416807 (1995-05-01), Brady et al.
patent: 5623265 (1997-04-01), Pawar et al.
patent: 5756999 (1998-05-01), Parrish et al.
patent: 5801657 (1998-09-01), Fowler et al.
patent: 5856800 (1999-01-01), Le Pailleur et al.
Milgrome et al. A monolithic CMOS . . . Converter Integrated Circuit, IEEE Transactions on Nuclear Science, vol. 40, No. 4, PP 721-723, Aug. 1993.*
Co-pending U.S. Patent Application, Serial No. 08/981,109, filed May 26, 1998, Neal R. Butler, “Digital Offset Corrector”, Attorney Docket No.: L0501/7021.
Co-pending U.S. Patent Application, Serial No. 09/011,942, filed Aug. 24, 1998, Neal R. Butler “Bolometric Focal Plane Array”, Attorney Docket No.: L0501/7022.
Co-pending U.S. Patent Application, Serial No. 09/051,180, filed Sep. 14, 1998, Neal R. Butler “Uncooled Focal Plane Array Sensor”, Attorney Docket No.: L0501/7023.
1992 IEEE Nuclear Science Symposium And Medical Imaging Conference (NSS/MIC '92), Orlando, FL, USA, Oct. 25-31, 1992, vol. 40, No. 4, pt. 1, Transactions On Nuclear Science, Aug. 1993, pp 721-723 Milgrome O.B., et al., “A Monolithic CMOS 16 Channel, 12 bit, 10 Microsecond Analog To Digital Converter Integrated Circuit”.
Euromicro 85, Short Notes, Brussels, Belgium, Sep. 3-6, 1985, vol. 16, No. 2-3, Microprocessing & Microprogramming, Sep.-Oct. 1985, Netherlands, pp 95-99, Vranes P.A., “An Implementation Of A High Speed Gray To Binary Code Converter”.
IEEE Transactions On Nuclear Science, vol. 36, No. 1, Feb. 1, 1989, pp 646-649, Cousins R.D., et al. “32-Channel Digital 6-Bit TDC With 2.5 NS Least Count”.
Jean-Pierre Peguy
Lockheed-Martin IR Imaging Systems, Inc.
Wolf Greenfield & Sacks P.C.
LandOfFree
Metastability resolved monolithic analog-to-digital converter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metastability resolved monolithic analog-to-digital converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metastability resolved monolithic analog-to-digital converter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2544616