Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2005-06-17
2011-11-29
Fahmy, Wael M (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S734000, C257S777000, C257S698000
Reexamination Certificate
active
08067837
ABSTRACT:
A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.
REFERENCES:
patent: 4087314 (1978-05-01), George
patent: 4179802 (1979-12-01), Joshi
patent: 4652336 (1987-03-01), Andrascek
patent: 5061985 (1991-10-01), Meguro
patent: 5071518 (1991-12-01), Pan
patent: 5083187 (1992-01-01), Lamson
patent: 5108950 (1992-04-01), Wakabayashi
patent: 5132775 (1992-07-01), Brighton
patent: 5134460 (1992-07-01), Brady
patent: 5137845 (1992-08-01), Lochon
patent: 5223454 (1993-06-01), Uda
patent: 5226232 (1993-07-01), Boyd
patent: 5261155 (1993-11-01), Angulas
patent: 5268072 (1993-12-01), Agarwala
patent: 5326709 (1994-07-01), Moon
patent: 5418186 (1995-05-01), Park
patent: 5503286 (1996-04-01), Nye, III
patent: 5541135 (1996-07-01), Pfeifer
patent: 5554940 (1996-09-01), Hubacher
patent: 5565379 (1996-10-01), Baba
patent: 5600180 (1997-02-01), Kusaka
patent: 5631499 (1997-05-01), Hosomi
patent: 5656858 (1997-08-01), Kondo et al.
patent: 5656863 (1997-08-01), Yasunaga
patent: 5664642 (1997-09-01), Williams
patent: 5729896 (1998-03-01), Dalal et al.
patent: 5736791 (1998-04-01), Fujiki
patent: 5756370 (1998-05-01), Farnworth
patent: 5766982 (1998-06-01), Akram et al.
patent: 5767010 (1998-06-01), Mis
patent: 5854513 (1998-12-01), Kim
patent: 5877078 (1999-03-01), Yanagida
patent: 5883435 (1999-03-01), Geffken
patent: 5892273 (1999-04-01), Iwasaki
patent: 5898222 (1999-04-01), Farooq
patent: 5903343 (1999-05-01), Ning
patent: 5943597 (1999-08-01), Kleffner
patent: 5946590 (1999-08-01), Satoh
patent: 5985765 (1999-11-01), Hsiao
patent: 6013571 (2000-01-01), Morrell
patent: 6028363 (2000-02-01), Lin
patent: 6042953 (2000-03-01), Yamaguchi
patent: 6075290 (2000-06-01), Schaefer
patent: 6077726 (2000-06-01), Mistry
patent: 6093964 (2000-07-01), Saitoh
patent: 6144100 (2000-11-01), Shen
patent: 6144102 (2000-11-01), Amagai
patent: 6162652 (2000-12-01), Dass
patent: 6180265 (2001-01-01), Erickson
patent: 6187680 (2001-02-01), Costrini
patent: 6194309 (2001-02-01), Jin
patent: 6197613 (2001-03-01), Kung
patent: 6198619 (2001-03-01), Fujioka
patent: 6229220 (2001-05-01), Saitoh
patent: 6229711 (2001-05-01), Yoneda
patent: 6238599 (2001-05-01), Gelorme et al.
patent: 6250541 (2001-06-01), Shangguan
patent: 6271107 (2001-08-01), Massingill
patent: 6319830 (2001-11-01), Yamaguchi
patent: 6323426 (2001-11-01), Hoshizaki et al.
patent: 6332988 (2001-12-01), Berger, Jr.
patent: 6362087 (2002-03-01), Wang
patent: 6372622 (2002-04-01), Tan
patent: 6380061 (2002-04-01), Kobayashi
patent: 6406967 (2002-06-01), Chung
patent: 6426281 (2002-07-01), Lin
patent: 6426556 (2002-07-01), Lin
patent: 6429531 (2002-08-01), Mistry
patent: 6452270 (2002-09-01), Huang
patent: 6467674 (2002-10-01), Mihara
patent: 6479900 (2002-11-01), Shinogi
patent: 6495397 (2002-12-01), Kubota
patent: 6501169 (2002-12-01), Aoki
patent: 6518651 (2003-02-01), Hashimoto
patent: 6573598 (2003-06-01), Ohuchi
patent: 6578754 (2003-06-01), Tung
patent: 6592019 (2003-07-01), Tung
patent: 6600234 (2003-07-01), Kuwabara
patent: 6627988 (2003-09-01), Andoh
patent: 6653563 (2003-11-01), Bohr
patent: 6661100 (2003-12-01), Anderson
patent: 6683380 (2004-01-01), Efland
patent: 6707159 (2004-03-01), Kumamoto
patent: 6709985 (2004-03-01), Goruganthu
patent: 6731003 (2004-05-01), Joshi
patent: 6732913 (2004-05-01), Alvarez
patent: 6762122 (2004-07-01), Mis
patent: 6809020 (2004-10-01), Sakurai
patent: 6815324 (2004-11-01), Huang
patent: 6853076 (2005-02-01), Datta
patent: 6861742 (2005-03-01), Miyamoto
patent: 6864165 (2005-03-01), Pogge
patent: 6940169 (2005-09-01), Jin
patent: 6998710 (2006-02-01), Kobayashi
patent: 7008867 (2006-03-01), Lei
patent: 7034402 (2006-04-01), Seshan
patent: 7098127 (2006-08-01), Ito
patent: 7135766 (2006-11-01), Costa
patent: 7220657 (2007-05-01), Ihara
patent: 7246432 (2007-07-01), Tanaka
patent: 7335536 (2008-02-01), Lange
patent: 7405149 (2008-07-01), Lin et al.
patent: 7456089 (2008-11-01), Aiba
patent: 7462942 (2008-12-01), Tan
patent: 2001/0040290 (2001-11-01), Sakurai
patent: 2002/0043723 (2002-04-01), Shimizu
patent: 2002/0127836 (2002-09-01), Lin et al.
patent: 2003/0006062 (2003-01-01), Stone
patent: 2003/0111711 (2003-06-01), Lin et al.
patent: 2003/0133055 (2003-07-01), Um et al.
patent: 2003/0137058 (2003-07-01), Magerlein et al.
patent: 2003/0218246 (2003-11-01), Abe
patent: 2004/0007779 (2004-01-01), Arbuthnot
patent: 2004/0070086 (2004-04-01), Lee et al.
patent: 2004/0126927 (2004-07-01), Lin et al.
patent: 1536469 (2005-06-01), None
patent: 60217646 (1985-10-01), None
patent: 62160744 (1987-07-01), None
patent: 1061038 (1989-03-01), None
patent: 03022437 (1991-01-01), None
patent: 4278543 (1992-10-01), None
patent: 4318935 (1992-11-01), None
patent: 8013166 (1996-01-01), None
patent: 10107064 (1998-04-01), None
patent: 2000260803 (2000-09-01), None
patent: 2002016096 (2002-01-01), None
patent: 2003133477 (2003-05-01), None
patent: 2003234367 (2003-08-01), None
patent: 2003282788 (2003-10-01), None
patent: 2006128662 (2006-05-01), None
patent: 2006147810 (2006-06-01), None
patent: 584950 (2004-04-01), None
patent: WO 87/01509 (1987-03-01), None
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369-373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 773-776.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session
Fahmy Wael M
McDermott Will & Emery LLP
Megica Corporation
Salerno Sarah K
LandOfFree
Metallization structure over passivation layer for IC chip does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metallization structure over passivation layer for IC chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metallization structure over passivation layer for IC chip will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4281537