Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-09-02
2002-09-10
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S758000, C257S700000, C257S701000, C257S208000, C257S207000, C257S691000, C257S664000, C257S775000, C257S210000
Reexamination Certificate
active
06448591
ABSTRACT:
BACKGROUND OF THE INVENTION
The Field of the Invention
The present invention relates to the fabrication of microelectronic semiconductor devices. More particularly, the present invention relates to the fabrication of metallization lines. In particular, the present invention relates to a metallization line layout optimization to avoid depth of field sensitivity and excess reflectance in isolated metallization lines. Additionally, the present invention achieves a substantially planar dielectric layer upper surface, upon deposition and without further processing, of the dielectric layer over the inventive metallization line layout.
The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductive substrates described above. Following the formation of semiconductor devices, the devices need to be electrically connected, either to themselves or to the outside world to make the semiconductor device function as part of a greater whole. The electrical connection of the semiconductor devices is carried out by the metallization process. Metallization comprises the layout and patterning of a series of electrically conductive lines upon an upper surface of a substrate. The metallization lines make electrical connection, through either vias or interconnects, between individual semiconductor devices and/or the outside world.
FIG. 1
illustrates a plan view of a typical “Manhattan” style metallization line layout
10
, by way of non-limiting example, at least a portion of a metal-1 layout for a sense amplifier. A Manhattan style metallization layout may also be called a rectangular, or right-angle rectilinear metallization layout. Such a metallization layout is characterized by raised, elongate structures that have only substantially right-angle deviations from being straight or linear. The term “vertical” is intended to mean a direction between the top and bottom of the page of a figure. The term “lateral” is intended to means a sideways direction of a figure, substantially orthogonal to “vertical.”
Referring to
FIG. 1
, arbitrary region Z is seen in
FIG. 1
to have a substantially rectangular shape that includes parallel vertical boundaries
15
,
15
′ and parallel horizontal boundaries
17
,
17
′. Metallization lines include isolated lines and may be shown as having an end
11
within an arbitrary region Z. Metallization lines include continuous lines and are shown as extending substantially across
FIG. 1
with no end found within arbitrary region Z. For example, isolated line
1
-left (isolated line
1
L) is defined as having end
11
within arbitrary region Z of metallization line layout
10
, and arbitrary region Z does not include a physical edge of metallization line layout
10
. An “end”
11
is defined as a portion of a metallization line that discontinues within arbitrary region Z and that has a length that may be substantially the width W of the metallization line for a length along the same metallization line at least equal to the distance W.
It is noted that in the prior art “Manhattan” layout of metallization line layout
10
, ends
11
for all of isolated lines
1
R-
11
R are all a fixed distance
27
from a closest vertical boundary
15
of arbitrary region Z, or a fixed distance
29
from a closest boundary
15
′.
A continuous line is defined as having no end within arbitrary region Z of metallization line layout
10
. For example, continuous line
3
has no end within arbitrary region Z depicted as FIG.
1
. Continuous line
3
has an enlarged feature
13
.
FIG. 1
illustrates several occurrences of isolated lines and continuous lines. As used herein, an “intersection” is defined as a subregion within arbitrary region Z at which at least one end of a metallization line occurs. The four top-most metallization lines in
FIG. 1
are demarcated as isolated lines
1
L and
2
L and isolated lines
1
R and
2
R. The next metallization line down is a continuous metallization line and is thus demarcated as continuous line
3
.
An intersection is defined as a portion of a layout with at least one end
11
. The intersection may be bordered by a continuous line. For example, a 6-way intersection occurs at the demarcation X where it can be seen that a 6-arrowed illustrative figure has been drawn to demonstrate the 6-way nature of this intersection. Intersection X is bordered by continuous lines
6
and
9
. Intersection X includes the spaces between continuous line
6
, isolated line
7
L, isolated line
8
L, isolated line
7
R, isolated line
8
R, and continuous line
9
.
A 4-way intersection may be considered as occurring at the demarcation Y where it can be seen that a 4-arrowed illustrative figure has been drawn. The 4-way intersection is thus defined as an open region having ends
11
, that has a clear line of sight, for example between isolated lines
10
L and
11
L, between isolated lines
10
L and
10
R, between isolated lines
10
and
11
R, and between isolated lines
11
R and IL. A 3-way intersection may be considered as occurring in
FIG. 1A
at the demarcation V where it can be seen that a 3-arrowed illustrative figure has been drawn near end
11
. This intersection is thus created by an open region that has a clear line of sight between isolated line
2
L and continuous line
1
, between continuous line
1
and continuous line
3
, and between continuous line
3
and isolated line
2
L. Thus, by this definition, an intersection represents the space between a plurality of metallization lines, wherein at least one metallization line has an end that creates at least a portion of the space therebetween.
The metallization lines have been fabricated in the past at a minimum width and as far apart as possible in order to avoid the problems of capacitative coupling and shorting. While the advantages of avoiding capacitative coupling and shorting are preferred, the everincreasing pressure to miniaturize microelectronic devices influences the design engineer to decrease the overall scale of a metallization line layout. This decrease gives rise to at least three significant problems for the process engineer.
The first significant problem is the focus offset sensitivity or depth of field capability of existing photolithographic exposure equipment. The equipment's focus offset sensitivity may cause significant problems during patterning of isolated metallization lines. As photolithographic exposure wavelengths become less optimal due to the ever-decreasing scale of the layout, focus offset sensitivity will blur the edges of the metallization line mask. Thereby the entire exposure of the metallization line mask may be excessively blurred, the mask may fail to form, and no metallization line may result. Excessive blurring can cause the problem of an open circuit. This problem may be overcome by widening metallization lines, but widening can be detrimentally offset by the likelihood of short circuiting across metallization lines because nearby closest features may bridge and short or contaminant particles may bridge between metallization lines and create a short circuit.
The second significant problem occurs during fabrication of the metallization lines due to undesired exposure to the masking material and the excess reflectance problems caused by photolithographic light. Light exposure with excess reflectance results in the lateral thinning and/or the recession of a metallization line end of the masking material. Hence, either a thinned, receded,
Micro)n Technology, Inc.
Williams Alexander O.
Workman & Nydegger & Seeley
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