Metallization and wire bonding process for manufacturing power s

Details Metallization and wire bonding process for manufacturing power s Metallization and wire bonding process for manufacturing power s

1996-07-29

1999-02-09

Graybill, David

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

438599, 438611, 438612, 438665, 438669, 438694, 438761, 438778, 2281805, H01L 21283, H01L 2160

Patent

active

058693572

ABSTRACT:
A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between components previously defined; a step of depositing a layer of passivating material over the entire surface of the chip; a step of selectively etching of the layer of passivating material down to the first metal layer to define bonding areas represented by uncovered portions of the first metal layer; a step of depositing of a thick second metal layer over the entire surface of the chip; a step of selectively etching of the second metal layer down to the layer of passivating material to remove the second metal layer outside the bonding areas; and a step of connecting bonding wires to the surface of the second metal layer in correspondence of said bonding areas.

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