Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2001-02-02
2001-09-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
C438S393000
Reexamination Certificate
active
06284617
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority from a provisional application, Ser. No. 60/064,865, filed Nov. 5, 1997, which is hereby incorporated by reference. However, the content of the present application is not identical to that of the priority application.
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates generally to electronic circuits, especially to radio frequency (RF) MOS devices, having improved capacitors and inductors. A schematic diagram of an RF-MOS circuit is shown in FIG.
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Background: Inductors
One of the basic problems in integrating inductors into semiconductor devices is the parasitic capacitances which are produced between the inductor and the substrate. A typical inductor is formed by taking the layers of metallization, tying them all together and stacking them. However, since the first layer of metallization is close to the substrate, a large capacitance is formed between the inductor and the substrate. In order to maximize the Q value, (the ratio of the inductive reactance to its effective series resistance), it is preferable that the inductor be as far away from the substrate as possible. Furthermore, it is desirable for the metal line of the inductor to have some height so that there will be magnetic coupling between the coils. With aluminum wiring, the metals are thin because it is difficult to planarize the wires if it is very thick. Hence, each metallization layer is quasi-planar, so the inductors are wound with flat spirals which results in magnetic flux leaking out.
Background: Capacitors
Usually, capacitors constructed within integrated circuit (IC) chips use one of the following combinations to form the plates of the capacitors: a) the substrate and a polysilicon layer, b) two separate polysilicon layers, or two different metallization layers. One problem with these capacitors is that their location inside of the package allows capacitive coupling to the substrate. Additionally, the poly-poly capacitor has inherent series resistance in each plate.
Innovative Structures and Methods
The present application discloses formation of an integrated inductor and an integrated capacitor using a thick copper layer on the outside of the protective overcoat. This has the advantage of removing the inductor as far from the substrate as possible, thereby reducing the parasitic capacitances. Using a thick copper layer outside the protective overcoat also has the advantage of using the free area above the package to construct a capacitor, which additionally has a low series resistance. Furthermore, because both the inductor and the capacitor can be constructed outside the protective overcoat, radio frequency (RF) drive circuits can be constructed outside the chip.
REFERENCES:
patent: 5071518 (1991-12-01), Pan
patent: 5240879 (1993-08-01), DeBruin
patent: 5744832 (1998-04-01), Wolters et al.
Culbertson et al., “Evolution of RFMOS™ Power Amplifiers for High Efficiency Digital Cellular Applications,” Texas Instruments, Dallas, Texas, Publishing date unknown.
Brauchler et al., “Performance of RFMOS™ for 1.9 GHz CDMA Operation,” IEEE MTT-S International Microwave Symposium, Jun. 1998.
Khatibzadeh et al., “RF Technology Trends in Digital Wireless Communications,” Texas Instruments, Dallas, Texas, Publishing date unknown.
Arch John Kenneth
Erdeljac John P.
Hutter Louis Nicholas
Khatibzadeh M. Ali
Brady III Wade James
Telecky Jr Frederick J.
Texas Instruments Incorporated
Tsai Jey
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