Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-08-29
2006-08-29
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C257S208000, C257S758000
Reexamination Certificate
active
07099174
ABSTRACT:
A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.
REFERENCES:
patent: 4295149 (1981-10-01), Balyoz et al.
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5621679 (1997-04-01), Seo et al.
patent: 5650975 (1997-07-01), Hamade et al.
patent: 5699308 (1997-12-01), Wada et al.
patent: 5751031 (1998-05-01), Thompson et al.
patent: 5808930 (1998-09-01), Wada et al.
patent: 6125070 (2000-09-01), Tomishima
patent: 6184122 (2001-02-01), Fu et al.
patent: 6314011 (2001-11-01), Keeth et al.
patent: 6339549 (2002-01-01), Jinbo et al.
patent: 6445065 (2002-09-01), Gheewala et al.
patent: 2002/0011610 (2002-01-01), Ishimaru et al.
Merritt Todd A.
Thompson J. Wayne
Dickstein & Shapiro LLP
Nguyen Van-Thu
LandOfFree
Metal wiring pattern for memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Metal wiring pattern for memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Metal wiring pattern for memory devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3715901