Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Utility Patent
1999-07-08
2001-01-02
Wong, Don (Department: 2821)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S758000, C257S784000
Utility Patent
active
06169326
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a metal wire for a semiconductor integrated circuit, and more particularly to a metal wire of a semiconductor device and a method for forming the same that improves the resistance characteristics of the wire and its reliability by self-aligning a conductive line and a contact hole.
Generally, aluminum (and its alloy) thin films are widely used as a metalization material in semiconductor devices because of their high conductivity, facility in forming a pattern by dry-etching, and good adhesion to silicon oxide layers. Additionally, aluminum is a relatively low cost material.
As the desire for integration of the semiconductor device increases, the size of the circuit decreases and its metal wire is miniaturized and multi-layered, so that the importance of step coverage increases in the portion of the device having a topology and a contact hole such as a via hole.
If sputtering is used to apply the metalization material, the metal wire layer on an undulated area becomes partially thinned by a shadow effect, and especially on the contact hole area where an aspect ratio is greater than 1.
Therefore, instead of using a physical vapor deposition (“PVD”) method, a lower pressure chemical vapor deposition (“LPCVD”) method is used to apply the metalization layer which is capable of depositing the metal wire layer in a uniform thickness. Studies have been conducted for improving step coverage by forming a tungsten layer using a LPCVD method. However, since the resistivity of the tungsten metal wire layer is at least two times greater than an aluminum metalization layer, tungsten is not a practical material for forming a metalization layer.
At the same time, improved methods for forming plug layers in a contact hole have been developed.
In one method, the plug layer is formed by selectively growing a tungsten layer through a substrate exposed on the contact hole by selective CVD.
Another method for forming the plug layer includes using a barrier metal layer or glue layer on which a tungsten layer is formed over the surface of the barrier metal layer, and or glue layer. Thereafter, the layer is etched back.
However, with the selective CVD method and the etch-back method, after depositing the tungsten on the overall surface, it is required to form a reliable barrier or adhesion layer in the contact hole having a high aspect ratio.
For this purpose, it is important to obtain the minimum thickness at which the core of the tungsten can be generated, on the bottom or side walls of the contact hole by a collimator or CVD process.
The depth of the contact hole varies with the planarization of the insulating layer, so that the surfaces of the contact hole and plug layer are not integrally formed, but the surface of the buried layer is actually formed to be lower than the surface of the contact hole.
As an alternative for aluminum, copper has a lower resistance and possesses good characteristics for resisting eletromigration and stressmigration, which can collectively improve reliability of the metal wire. Studies of forming a metal wire with Cu by sputtering or CVD methods have also been performed.
However, Cu has its own over inherent disadvantages. For example, when a method using a halogen compound (which is useful when etching aluminum), is applied to a metal wire using Cu, the evaporating pressure of the Cu-halogen compound is low, such that its working temperature must be increased to nearly 500° C. to achieve an acceptable etch rate.
There have been two methods which utilize Cu. One method includes forming a trench in the form of a metalization pattern instead of a direct patterning by etching. A Cu layer is deposited on an insulating layer and then a buried conductor line is formed by etching back through CMP (chemical mechanical polishing). Another method using Cu calls for forming a selective plug layer by vertical growth in which a lower conductive layer is used as a seed in a contact hole such as a via hole.
Currently, because the width of the conductive line and the size of the contact hole are reduced with the increasing integration of a semiconductor device, the margin for alignment of the conductive line with the contact hole becomes an increasingly important consideration in order to prevent a decrease in the resistance of the metal wire and its reliability. That is, if the conductive line and contact hole are misaligned, their contact area is reduced, and the current density is increased. Thus, the reliability is declined. Moreover, because the alignment interval is actually decreased, cross-talk occurs. Further, as parasitic capacitance increases, the operational speed of the circuit is reduced. To solve the alignment problem, the technique of self-aligned contacts was developed by NEC Co. in 1992, IEDM., p. 305.
FIGS. 1A
to
1
D illustrate a conventional procedure for manufacturing a metal wire.
The self-aligned contact technique described is a. planarized buried metal wire method in which the corners of the contact hole are self-aligned in the trench in parallel to the conductive line so that the contact holes are aligned only in the direction of the width of the conductive line.
As illustrated in
FIG. 1A
, an etch-stop layer
2
is formed on a planarized insulating layer
1
. The two layers are created on a semiconductor substrate (not shown) on which a device is completely formed.
As illustrated in
FIG. 1B
, the etch-stop layer
2
and insulating layer
1
, laid under the etch-stop layer
2
, are selectively etched to form trenches
3
.
As illustrated in
FIG. 1C
, a photoresist layer
4
is then deposited and patterned. The insulating layer
1
is selectively removed using the patterned photoresist layer
4
as a mask to form self-aligned contact hole
5
. Here, the pattern of one of the trenches
3
and contact hole
5
are formed so as to overlap with each other.
As illustrated in
FIG. 1D
, a metal layer made of tungsten is buried in the trenches
3
and the contact hole
5
. The dashed lines show the configuration of the metal layers as contained in the insulating material
1
. The combination is then etched back by CMP to form the plug and buried metal wires
6
.
However, a conventional metal wire formed using the described self-aligned contact technique has the following inherent problems.
The primary problem is that the photo-lithography etching process must be performed twice (2) to form the trench and contact hole. Having to repeat this procedure step twice both increases the possibility of nonalignment and increases the costs of manufacturing.
Additionally, while the contact hole is self-aligned in the horizontal direction of the conductive line corresponding to the trench, the contact hole may not self-aligned in the vertical direction. The possibility of misalignment increases as the interval between the metal wires becomes narrow.
SUMMARY OF THE INVENTION
An object of the invention is to solve the above-discussed problems and to provide a metal wire of a semiconductor device and its formation method for improving the resistance characteristics of the wire and its reliability for self-alignment.
The metal wire of a semiconductor device of the invention includes: an insulating layer; a contact plug buried in the insulating layer for coupling to a lower metal wire or impurity diffusion area; a first pattern layer buried in the insulating layer and in contact with the contact plug to be thereby formed; and at least one second pattern layer formed within the first pattern layer in the form of an island.
The invention also is directed to a method for forming a metal wire of a semiconductor device, comprising the steps of forming an insulating layer and first etch-stop layer on a substrate forming a first trench having sidewalls and a bottom by selectively removing portions of said first etch-stop layer forming a second etch-stop layer on the insulating layer, including the first trench, and first-etch stop layer etching back said second etch-stop layer from within the trench to form a mask from said fir
Hyundai Electronics Industries Co,. Ltd.
Nguyen Hoang
Wong Don
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