Metal-to-metal antifuse including etch stop layer

Details Metal-to-metal antifuse including etch stop layer Metal-to-metal antifuse including etch stop layer

1993-12-21

1995-01-10

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257 50, 257754, 257757, 437292, 437293, 437295, 437922, H01L 2702, H01L 2348

Patent

active

053810350

ABSTRACT:
According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via. Thus the partially etched second a-Si layer forms a part of the second metallization layer and the Nitride/a-Si/Nitride insulating antifuse layer has a constant thickness determined by the process used to lay it down, rather than on the more uncontrollable etch process. Accordingly, the programming voltage of the antifuse is more predictable than with prior art antifuse structures.

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G. H. Chapman et al., "A Laser Linking Process for Restructurable VLSI", CLEO '82 (Apr. 1982) 5 pages.
K. S. Ravindhran et al. "Field Programmable Gate Array (FPGA) Process Design for Multilevel Metallization Technology", VMIC Conference, Jun. 8-9, 1993, pp. 62-64.

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