Metal to amorphous silicon to metal anti-fuse structure

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257 50, 257208, 257530, 438600, H01L 2994

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active

060160012

ABSTRACT:
An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.

REFERENCES:
patent: 5374832 (1994-12-01), Tung et al.
patent: 5514900 (1996-05-01), Iranmanesh
patent: 5576576 (1996-11-01), Hawley et al.

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