Metal staples to prevent interlayer delamination

Details Metal staples to prevent interlayer delamination Metal staples to prevent interlayer delamination

1997-09-30

1999-11-02

Williams, Alexander Oscar

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257758, 257773, 257723, 257620, 257700, 257734, H01L 2348, H01L 2352, H01L 2940

Patent

active

059776390

ABSTRACT:
The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls.

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