Metal sealed wafer level CSP

Details Metal sealed wafer level CSP Metal sealed wafer level CSP

2011-04-26

2011-04-26

Sefer, A. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S620000, C257SE23169

Reexamination Certificate

active

07932602

ABSTRACT:
A semiconductor device comprising: (a) a semiconductor substrate having a dicing region circumscribing a chip region, the chip region including a central region and a peripheral region around the central region; (b) an active electrical structure formed to extend from a first main surface to a second surface vertically spaced apart from the last main surface in the central region of the semiconductor substrate; (c) a through dummy isolation structure formed within the peripheral region to extend from the first main surface of the semiconductor substrate to a third surface vertically spaced apart from the first main surface of the semiconductor substrate, the through dummy isolation structure surrounding the active electrical structure; (d) an insulating layer disbursed throughout the active electrical structure within the central region and around the through dummy isolation structure of the peripheral region, the insulating layer including top and opposed peripheral sides; and (e) a metal film located over the top and peripheral sides of the wiring insulating film and over the semiconductor substrate.

REFERENCES:
patent: 2005/0164490 (2005-07-01), Morrow et al.
patent: 2006/0145347 (2006-07-01), Aida
patent: 2006/0255465 (2006-11-01), Kishiro
patent: 2002-359257 (2002-12-01), None
patent: 2009-43779 (2009-02-01), None

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