Metal programmable self-timed memories

Details Metal programmable self-timed memories Metal programmable self-timed memories

2008-06-17

2010-06-29

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S205000, C365S230060, C365S051000, C365S063000, C365S233500

Reexamination Certificate

active

07746722

ABSTRACT:
A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.

REFERENCES:
patent: 6229746 (2001-05-01), Tooher
patent: 6542434 (2003-04-01), Monzel
patent: 6674661 (2004-01-01), Becker
patent: 6870777 (2005-03-01), Maki
patent: 6876587 (2005-04-01), Ashizawa et al.

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