Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2005-06-07
2005-06-07
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000
Reexamination Certificate
active
06902957
ABSTRACT:
A method for forming a metal programmable integrated circuit that can use a plurality of clock sources and balance clock skew. The integrated circuit has a semiconductor body. The method includes step (a) used for forming a plurality of basic units on the semiconductor body wherein each basic unit has at least a logic module, at least a driving module, and at least a storage module, and step (b) used for forming a metal layer for programming the logic module to be able to perform logic operations, programming the driving module to able to drive an input signal inputted into the driving module, and programming the storage module to be able to store data after performing step (a).
REFERENCES:
patent: 4319396 (1982-03-01), Law et al.
patent: 6312980 (2001-11-01), Rostoker et al.
Shieh Shang-Jyh
Wang Hsin-Shih
Faraday Technology Corp.
Harrison Monica D.
Hsu Winston
Pert Evan
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