Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1998-12-15
2001-06-26
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S022000, C257S183000, C257S629000, C257S631000
Reexamination Certificate
active
06252262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to passivating layers for III-V semiconductors.
2. Related Art
Gallium arsenide semiconductors, as well as other III-V semiconductors, have become increasingly popular because of their extremely high speeds of operation and high operating frequencies. However, many III-V materials, including GaAs, are sensitive to surface effects. Mid-gap states are created near the surface of the material which result in high surface recombination velocities for free carriers, an accompanying decrease in carrier lifetimes, and Fermi level pinning. In GaAs devices, it is believed that midgap states are created by As atoms near the surface/interface which have dangling bonds or occupy positions in the lattice which should be occupied by Ga atoms.
Much effort has been made to develop procedures which effectively passivates the exposed surfaces of III-V materials, most notably GaAs. A variety of surface treatments have been attempted with limited Success. These include wet chemical application of a sulphur surface layer (see C. J. Sandroffet al., Appl. Phys. Lett. 50,256 (1987); and J. F. Fan, H. Oigawa and Y. Nannichi, Jpn. J. Appl. Phys. 27, L1331 (1988) or a selenium surface layer (see C. J. Sandroff et al., J. Appl. Phys. 67, 586 (1990), and S. Belkouch et al., Solid State Elect. 39,507 (1996)) or in-situ growth of a selected oxide (see M. Passlack et al., Appl. Surf. Sci. 104/105, 441 (1996)) to inhibit the formation of surface mid-gap states. A number of patents relate to passivating layers for GaAs semiconductors including, for example, U.S. Pat. Nos. 4,546,372 (Shuskus), 5,550,089 (Dutta et al.), 5,539,248 (Abrokwah et al.) and 5,686,756 (Hori). One particular passivating layer for III-V semiconductor materials of interest here is that disclosed in U.S. Pat. No. 4,828,935 (Jonker et al), the disclosure of which is hereby incorporated by reference. The passivating layer is formed of Zn and Se as the active components and the patent is of interest because of the disclosure therein states that the passivating layer may include a quantity of Fe. However, the Fe is not an active component, but is rather used to widen the bandgap of the material, and the passivating layer has structural defects which are disadvantageous.
Si CMOS (complementary metal-oxide-semiconductor) technology currently dominates the low power and digital industries due to its low power attributes. The existence of a stable native oxide, SiO2, which provides an insulating surface layer with minimal effect on the properties of the underlying Si, has been the key enabling ingredient. There is great interest in utilizing GaAs (and related compounds, e.g. AlGaAs, InGaAs) for such applications rather than Si, since they offer both higher speed and lower power operation. However, in contrast to Si, there is no stable native oxide for GaAs currently available. The oxide which forms on the GaAs surface is unstable, and produces a high density of defect states at the GaAs/oxide interface, which significantly degrade performance. These states at the GaAs surface/interface act as scattering and/or trapping centers, limit carrier lifetimes, and pin the Fermi energy at midgap. These states are believed to be due to As which is released upon the formation of a Ga-related surface oxide and trapped near the interface. The lack of a stable insulating surface layer and the strong propensity for the formation of midgap interface states have been the key issues in preventing the implementation of GaAs-based metal oxide semi-conductor field effect transistor (MOSFET) or metal insulator semiconductor (MIS) devices. A GaAs MOSFET/MISFET remains the grail of GaAs electronics.
Several efforts have focused on obtaining MOS-type operation in GaAs by substituting a wider bandgap material such as AlGaAs for the oxide as the insulating gate layer, with some success. This requires a more complex heterostructure, with additional disadvantages in that AlGaAs is a semiconductor, not an insulator, and the high Al concentrations required (75%) produce new defect states in the material; these factors result in finite leakage current and limit the allowed gate voltage swing.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is a passivating layer for passivating the surfaces of III-V semiconductor materials. The passivating layer suppresses the density of midgap states localized near the surface of the III-V material and, as a result, reduces the recombination velocities for free carriers and prevents Fermi level pinning.
Another object of the invention is a stable insulating surface layer for III-V semiconductor materials, to allow e.g., fabrication of improved GaAs-based MIS devices.
In one aspect, the invention is a metal passivating layer, at least a full monolayer thick, on a III-V semiconductor material, where the metal in the metal passivating layer bonds with the atomic species in the semiconductor material at the interface to prevent the formation of Group V dangling bonds and/or antisite defects (e.g., As on a Ga lattice site or Ga on an As lattice site). The passivating layer preferably prevents oxygen from reacting with the atomic species in the semiconductor material. Preferred metals for the passivating layer include iron (Fe), gold (Au), manganese (Mn), and combinations thereof. Preferably, the metal has a base of at least one of these metals (at least 51 at % is one or more of these metals).
The III-V semiconductor material is preferably selected from the group consisting of Group III—arsenic compounds and Group III—arsenic phosphide compounds.
In one preferred implementation, the metal film is patterned laterally to provide a lateral modulation potential. For instance, the metal film may be patterned into an array of wires or dots.
Another aspect of the invention includes a metal passivating layer for III-V semiconductor material, where this metal is at least partially oxidized. The oxide may form an insulator for an MIS device. Alternatively, the metal layer may be covered with any of the insulating layers used in device fabrication, e.g., silicon oxide, silicon dioxide, or silicon nitride.
Other features and advantages of the invention will be set forth in, or apparent from, the following detailed description of the preferred embodiments of the invention.
REFERENCES:
patent: 4828935 (1989-05-01), Jonker et al.
B.T. Jonker et al., “Enhanced Carrier Lifetimes and Suppression of Midgap States in GaAs at a Magnetic Metal Interface”, Phys. Rev. Lett. 79(24) 4886-89 (Dec. 15, 1997).
M. Passlack et al., “Low Dit, Thermodynamically Stable Ga2O3-GaAs Interfaces: Fabrication, Characterization, and Modeling”, IEEE Trans. Electr. Dev. 44(2) 214-25 (Feb. 1997).
M. Passlack et al., “GaAs surface passivation using in-situ oxide deposition”, Appl. Surf. Sci 104/105 441-47 (1996).
Glembocki O. J.
Holm R. T.
Jonker B. T.
Collins D. M.
Karasek John J.
Marciniszyn Jane B.
Picardat Kevin M.
The United States of America as represented by the Secretary of
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