Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-12-22
2002-10-22
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S534000
Reexamination Certificate
active
06469568
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a MOS (Metal Oxide Semiconductor) transistor circuit and a semiconductor integrated circuit. The present invention relates, in particular, to a MOS transistor circuit and a semiconductor integrated circuit suitable for lower power consumption.
Along with the increased degree of integration of a large scale integrated circuit (LSI) and its higher-speed operation in recent years, there is a problem of higher LSI power consumption and thus power reduction is strongly required. Since the LSI power consumption is proportional to square of a power supply voltage, reducing the power supply voltage is effective to reduce power consumption. However, if only the power supply voltage is reduced, high-speed operation is disabled due to lower on-currents of a MOS transistor. To avoid this problem, the absolute value of the threshold voltage of the MOS transistor needs to be lowered as the power supply voltage is reduced. However, if the absolute value of the threshold voltage is lowered, the off-currents are increased by subthreshold currents of the MOS transistor.
As disclosed in Japanese Patent Publication No. Hei 8-12917, a method of controlling the threshold voltage of the MOS transistor with the voltage of a gate terminal by connecting a semiconductor substrate or well with which the MOS transistor is formed to the gate terminal is proposed as a MOS transistor circuit for relieving the problem of increased off-currents. That is, the semiconductor substrate or well with which an NMOS transistor
1
is formed and the gate terminal of the NMOS transistor
1
are connected as shown in FIG.
6
. When a voltage at which the NMOS transistor
1
is turned on (that is, a voltage which is positive relative to a source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently reduced and thereby the on-current increases. On the other hand, when a voltage at which the NMOS transistor
1
is turned off (that is, a voltage which is equal or negative relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced.
For example, the relationship between gate voltages Vgs of the NMOS transistor
1
and drain currents Ids can be set as shown in FIG.
7
. The on-current can be increased to 10
−4
A/&mgr;m, which is the same level as that of a usual MOS transistor having a low-threshold voltage, while the off-current can be reduced to 10
−10
A/&mgr;m as in the case of a usual MOS transistor having a high-threshold voltage.
It is noted that, although an NMOS transistor is exemplified in
FIG. 6
, this configuration is also applicable to a PMOS transistor. That is, when a voltage at which a PMOS transistor is turned on (that is, a voltage which is negative relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well with which the PMOS transistor is formed. Therefore, the absolute value of the threshold voltage is equivalently reduced and thereby the on-current increases. On the other hand, when a voltage at which the PMOS transistor is turned off (that is, a voltage which is equal or positive relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced.
A configuration shown in
FIG. 8
is obtained when a CMOS (complementary metal oxide semiconductor) inverter circuit is constituted by using MOS transistors formed with a semiconductor substrate or well connected to a gate terminal as described above. To simplify the description below, it will be assumed that both a PMOS transistor
3
and an NMOS transistor
4
have characteristics shown in FIG.
7
. The semiconductor substrate or well with which the PMOS transistor
3
and the NMOS transistor
4
are formed is connected to gate terminals of the PMOS transistor
3
and the NMOS transistor
4
(that is, an input terminal
5
of the CMOS inverter circuit). Voltages Vsubp, Vsubn of the semiconductor substrate or well are equal to the voltage Vin of the input terminal
5
.
Therefore, since a turn-on voltage is applied to the PMOS transistor
3
when the voltage Vin of the input terminal
5
is equal to the ground voltage Gnd, the absolute value of the threshold voltage is equivalently lowered and the on-current is increased to 10
−4
A/&mgr;m. Since a turn-off voltage is applied to the NMOS transistor
4
at the same time, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced to 10
−10
A/&mgr;m. On the other hand, since a turn-off voltage is applied to the PMOS transistor
3
when the voltage Vin of the input terminal
5
is equal to the power supply voltage Vdd, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced to 10
−10
A/&mgr;m. Since a turn-on voltage is applied to the NMOS transistor
4
at the same time, the absolute value of the threshold voltage is equivalently lowered and the on-current is increased to 10
−4
A/&mgr;m. Thus, the on-current of the PMOS transistor
3
or the NMOS transistor
4
turned on becomes 10
−4
A/&mgr;m and the driving current of the CMOS inverter circuit is increased to 10
−4
A/&mgr;m. The off-current of the NMOS transistor
4
or the PMOS transistor
3
turned off becomes 10
−10
A/&mgr;m and thereby the leakage current flowing from the power supply voltage terminal to the ground voltage terminal is reduced to 10
−10
A/&mgr;m.
As disclosed in Japanese Patent Laid-Open Publication No. 5-108194 as another MOS transistor circuit for relieving the problem of increased off-current, it is proposed that LSI is in an active state that switching operation is performed or a standby state that switching operation is not performed and that the absolute value of the threshold voltage of a MOS transistor is set to be low in the active state and high in the standby state.
In this case, the threshold voltage is switched by switching the voltage Vsub of a semiconductor substrate or well with which an NMOS transistor
11
is formed as shown in
FIG. 9. 12
denotes a select circuit. Vact is selected by a Select signal in an active state while Vstb is selected and outputted as Vsub in a standby state. In this case, if the voltage Vact and the voltage Vstb are set as Vact>Vstb, the absolute value of the threshold voltage of the NMOS transistor
11
is higher when the voltage Vstb is applied as Vsub than when voltage Vact is applied. By doing this, for example, the relationship between gate voltages Vgs and drain currents Ids of the NMOS transistor
11
can be set as shown in FIG.
10
. The on-current in the active state can be increased to 10
−4
A/&mgr;m while the off-current in the standby state can be reduced to 10
−12
A/&mgr;m.
It is noted that, although an NMOS transistor is exemplified in
FIG. 9
, but this configuration is also applicable to a PMOS transistor. That is, in the case of a PMOS transistor, if the voltage Vact and the voltage Vstb are set as Vact<Vstb, the absolute value of the threshold voltage of the PMOS transistor
11
is higher when the voltage Vstb is applied as the voltage Vsub of the semiconductor substrate or well than when the voltage Vact is applied.
The configuration shown in
FIG. 11
is obtained when a CMOS (complementary metal oxide semiconductor) inverter circuit is constituted by using MOS transistors capable of switching voltages of a semiconductor substrate or well as described above. To simplify the description below, it will be assumed that both a PMOS transistor
13
and an NM
Sato Yuichi
Toyoyama Shinji
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