Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-09-21
2003-04-22
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S243000, C438S246000, C438S386000
Reexamination Certificate
active
06551895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of capacitors in dynamic random access memory (DRAM) arrays and more specifically to the utilization of unused “Dummy” border areas of the DRAM arrays as capacitors and other useful structures.
2. Description of the Related Art
Large capacitors are often needed in very large scale integration (VLSI) circuits. However, such capacitors require a large amount of chip area. As the density of circuits increase, it becomes more difficult to allocate sufficient area for such capacitors.
VLSI circuits, such as dynamic random access memory (DRAM) arrays have uniform repeatable shape patterns which are formed by lithographic techniques. However, due to different pattern densities, the patterns along the edges of the array are slightly different than the patterns not located along the edge (e.g., the “edge” effect). For example, elements such as via contacts that are located near the edge of the array often have patterns after exposure which are smaller than those located in the middle of the array due to uneven pattern density.
To overcome this problem a few columns of “dummy” patterns are formed at the edge of the array. Therefore, there are no active devices located at the edge of the array and all active devices will have uniformly-patterned shapes. The dummy patterns formed along the edge of the array are normally tied to a certain voltage level (e.g., GND/Vdd) and are not used. For large arrays the area wasted by a the dummy patterns can be significant.
The invention utilizes the otherwise wasted areas to formed useful elements such as capacitors. Therefore the invention increases the effective utilization of the chip.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor structure (and method for manufacturing the same) comprising an active array of first elements having a first manufacturing precision, a peripheral region surrounding the active array, the peripheral region including second elements having a second manufacturing precision less than the first manufacturing precision, wherein the second elements are isolated from the active array and comprise passive devices for improving operations of the active array.
The active array comprises an active memory array including bitlines and active wordlines. The second devices comprise dummy wordlines, deep trench capacitors, dummy devices, etc. and the second manufacturing precision is insufficient to use the dummy wordlines as the active wordlines. More specifically, the second devices could be capacitors (decoupling capacitors or reservoir capacitors), resistors, diodes or inductors.
The invention could also include a voltage regulator connected to the array, wherein the second devices add capacitance to the voltage regulator. The voltage regulator could be a negative wordline voltage regulator or a boosted wordline voltage generator.
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Hsu Louis L.
Netis Dmitry
C. Li Todd M.
Chaudhuri Olik
International Business Machines - Corporation
McGinn & Gibb, P.C.
Toledo Fernando
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