Metal locking structures to prevent a passivation layer from del

Details Metal locking structures to prevent a passivation layer from del Metal locking structures to prevent a passivation layer from del

1997-09-30

2000-03-28

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

Schottky barrier

With means to prevent edge breakdown

257452, 257638, 257640, 257643, H01L 27095, H01L 3100, H01L 2358

Patent

active

060435518

ABSTRACT:
An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

REFERENCES:
patent: 5270256 (1993-12-01), Bost et al.
patent: 5459355 (1995-10-01), Kreifels
patent: 5517042 (1996-05-01), Kitamura

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