Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-03-15
2005-03-15
Lebentritt, Michael (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S752000
Reexamination Certificate
active
06867498
ABSTRACT:
A metal line layout which includes two separate control spaces to address capacitive issues along speed sensitive pathways in an integrated circuit structure without negatively impacting Werner Fill processing. One control space (i.e., DRCgap1) is for decreasing the spacing between various metal features to standardize such spacing, and a second control space (i.e., DRCgap2) is for addressing capacitance issues along speed sensitive pathways. Between speed sensitive pathways, spacing of added metal features provided to long parallel metal lines are maintained at the second control spacing DRCgap2. Spaces at the ends of such long parallel metal lines are reduced to the first control spacing DRCgap1in order to best fill three-way-intersections (TWIs) with subsequent depositions.
REFERENCES:
patent: 5494853 (1996-02-01), Lur
patent: 5667918 (1997-09-01), Brainerd et al.
patent: 5763955 (1998-06-01), Findley et al.
patent: 5789313 (1998-08-01), Lee
patent: 5790417 (1998-08-01), Chao et al.
patent: 5798298 (1998-08-01), Yang et al.
patent: 5866482 (1999-02-01), Lee
patent: 5905289 (1999-05-01), Lee
patent: 5915201 (1999-06-01), Chang et al.
patent: 5924006 (1999-07-01), Lur et al.
patent: 5937323 (1999-08-01), Orczyk et al.
patent: 5956618 (1999-09-01), Liu et al.
patent: 5965940 (1999-10-01), Juengling
patent: 5981384 (1999-11-01), Juengling
patent: 6239008 (2001-05-01), Yu et al.
patent: 6259115 (2001-07-01), You et al.
patent: 6309956 (2001-10-01), Chiang et al.
patent: 6340631 (2002-01-01), Chih-Po et al.
patent: 6351019 (2002-02-01), DeBrosse et al.
patent: 6358845 (2002-03-01), Lou
patent: 6365521 (2002-04-01), Shubert et al.
patent: 6441469 (2002-08-01), Chrysostomides et al.
patent: 6448591 (2002-09-01), Juengling
patent: 6608335 (2003-08-01), Dixit et al.
patent: 6696359 (2004-02-01), Ireland
Dinsmore & Shohl LLP
Lebentritt Michael
Micro)n Technology, Inc.
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