Metal line layout in a memory cell

Details Metal line layout in a memory cell Metal line layout in a memory cell

2006-05-31

2009-10-20

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S203000

Reexamination Certificate

active

07606057

ABSTRACT:
A memory cell includes polysilicon gates2running in a first direction. A sequence of layers metal lines includes a layer of bit lines4running in a second direction substantially orthogonal to the first direction followed by data lines6running in that second direction and then word lines8running in the first direction. The data lines6are precharged to a value which is held whilst the bit lines4are being used to sense data values stored within a memory cell.

REFERENCES:
patent: 5295105 (1994-03-01), Atsumi
patent: 6665203 (2003-12-01), Fujisawa et al.
patent: 6829186 (2004-12-01), Kanno et al.
patent: 7161823 (2007-01-01), Lee et al.
patent: 7286379 (2007-10-01), Sun

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