Metal line having a multi-layered diffusion layer in a...

Details Metal line having a multi-layered diffusion layer in a... Metal line having a multi-layered diffusion layer in a...

2011-01-25

2011-01-25

Stark, Jarrett J (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S627000, C257SE23163, C257SE21584

Reexamination Certificate

active

07875978

ABSTRACT:
A metal line having a multi-layered diffusion layer in a resultant semiconductor device is presented along with corresponding methods of forming the same. The metal line includes an insulation layer, a multi-layered diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The multi-layered diffusion barrier is formed on a surface of the metal line forming region defined in the insulation layer. The diffusion barrier includes a VB2layer, a CrV layer and a Cr layer. The metal layer is formed on the diffusion barrier which substantially fills in the metal line forming region of the insulation layer to eventually form the metal line.

REFERENCES:
patent: 2010/0038785 (2010-02-01), Cheng et al.
patent: 2003-017437 (2003-01-01), None
patent: 1020070056126 (2007-05-01), None

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