Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1996-02-27
1997-09-02
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257774, 257775, H01L 2348
Patent
active
056635990
ABSTRACT:
An integrated circuit incorporates a metal wiring line layout scheme which reduces the likelihood of incorporating holes through the passivation layer which covers the metal wiring line. Wiring lines are formed so as to have constant separation around bends in the wiring lines, typically by also increasing the width of the wiring lines around the bends. This layout reduces the likelihood of forming holes in the passivation layer between wiring lines. Holes are prevented near the ends of wiring lines either by providing dummy wiring lines offset from the ends of the wiring lines or by reducing the height of the wiring lines at the ends of the wiring lines. The ends of wiring lines can be sloped by providing dummy vias at the ends of the wiring lines and forming the ends of the wiring lines in the dummy vias.
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Stanley Wolf, Ph.D., "Silicon Processing for the VLSI Era," vol. 2: Process Integration, pp. 200-204.
Potter Roy
Thomas Tom
United Microelectronics Corporation
Wright William H.
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