Metal layer structure of semiconductor device

Details Metal layer structure of semiconductor device Metal layer structure of semiconductor device

2006-12-28

2009-02-24

Doan, Theresa T (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S758000, C257S775000, C257S776000, C257SE21597, C257SE21575

Reexamination Certificate

active

07495340

ABSTRACT:
A metal layer structure of a semiconductor memory device is disclosed. The metal layer structure includes: a first metal layer to be connected to a contact plug; and a plurality of a second metal layers that are formed in parallel at a second spaced distance around the first metal layer, wherein a spaced distance of the second metal layers nearest the first metal layer maintains the second spaced distance which is wider than a first spaced distance of the second metal layers around the contact plug, and the spaced distance of the second metal layer next to the first metal layer maintains a third spaced distance, which is narrower than the second spaced distance, and the spaced distance between adjacent second metal layers gradually decreases to eventually be equal to the first spaced distance, for the second metal layers farthest from the first metal layer. Accordingly, an alignment margin can be ensured without requiring more area, and the contact plug can be connected to the next metal layer, even if an alignment error is produced.

REFERENCES:
patent: 5976972 (1999-11-01), Inohara et al.
patent: 6781235 (2004-08-01), Givens
patent: 1997-0072314 (1997-11-01), None
patent: 1999-0065383 (1999-08-01), None
patent: 10-2004-0039593 (2004-05-01), None
patent: 10-0719694 (2007-05-01), None

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