Metal interconnection system with a planar surface

Details Metal interconnection system with a planar surface Metal interconnection system with a planar surface

1990-07-27

1992-01-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437192, 437977, H01L 2144, H01L 21443

Patent

active

050844148

ABSTRACT:
A process is described for electrically interconnecting electronic devices located on a surface through one or more planar linking layers consisting of conductors and dielectrics. A three-step additive process is disclosed for forming each planar linking layer. The process may be repeated in order to form the multiple linking layers required for complex VLSI circuits. Each layer is formed by a three step process of applying a uniform dielectric, removing the dielectric where the interconnections, including vias and lines, are to be made and then selectively depositing a conductor to form the interconnections.

REFERENCES:
patent: 3477872 (1969-11-01), Amick
patent: 3785862 (1974-01-01), Grill
patent: 3982316 (1976-09-01), Calhoun et al.
patent: 4330931 (1982-05-01), Liu
patent: 4349609 (1982-09-01), Takeda et al.
patent: 4367119 (1983-01-01), Logan et al.
patent: 4404235 (1983-09-01), Tarng et al.
patent: 4424671 (1984-01-01), Abbas et al.
patent: 4426765 (1984-01-01), Shahriary et al.
patent: 4532702 (1985-08-01), Gigante et al.
patent: 4566940 (1986-01-01), Itsumi et al.
patent: 4582563 (1986-04-01), Hazuki et al.
patent: 4584207 (1986-04-01), Wilson
Fathimulla, "Single-Step Lift-Off Process Using Chlorobenzene Soak on AZ4000 Resists", J. Vac. Sci. Technol. B, vol. 3, No. 1, Jan./Feb. 1985, pp. 25-27.
Homma et al., "Feature Size Limit of Liftoff Metallization Technology", IEEE Trans. on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 512-517.
Serikawa et al., "The Size Effect of Liftoff Metallization of Sputtered Aluminum Films", IEEE Trans. on Electron Devices, vol. ED-29, No. 5, May 1982, pp. 834-837.
International Electron Devices Meeting, 1983, Washington, 5th-7th Dec. 1983, pp. 550-553, IEEE, New York, U.S.; T. Moriya et al.: "A Planar Metallization Process-Its Application to Tri-Level Aluminum Interconnection".
Extended Abstracts, vol. 84, No. 1, 6th-11th May 1984, pp. 114-115, Pennington, New York, U.S.; K. C. Saraswat et al.: "Selective CVD of Tungsten for VLSI Technology".
Woodruff et al., Tungsten and Other Refractory Metals for VLSI Applications, Mat. Res. Soc. (1986), pp. 173-183.
Edel et al., IBM Tech. Dis. Bull., vol. 14, (May 1972), pp. 3837-3838.
Chen et al., "Photo-CVD for VLSI Isolation", J. Electrochem. Soc., vol. 131, Sep. 1984, pp. 2146-2151.
Rothman, "Process for Forming Passivated Metal Interconnection System with a Planar Surface", J. Electrochem. Soc., vol. 130, No. 5, p. 1131, 5/83.
"Thick Tungsten Films in Multilayer Conductor Systems: Properties and Deposition Techniques", R. S. Blewer, V. A. Wells, Proceedings of First International IEEE VLSI Multilayer Interconnection Conference, Jun. 21-22, 1984, p. 153.
"Selective Low Pressure Chemical Vapor Deposition of Tungsten", E. K. Broadbent, C. L. Ramiller, Journal of the Electrochem. Soc., vol. 131, No. 6, p. 1427, Jun. 1984.

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