Metal interconnect structures for use with integrated circuit de

Details Metal interconnect structures for use with integrated circuit de Metal interconnect structures for use with integrated circuit de

1995-11-30

1997-06-17

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257778, 257777, 257774, 257797, 257700, 257686, H01L 2714, H01L 2348, H01L 2346, H01L 2904

Patent

active

056400497

ABSTRACT:
An integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure without, however, contributing unduly to the overall size of the integrated circuit structure comprising the die or chip. The one or more layers of metal interconnects are formed on the second substrate by the steps of forming a pattern of metal contacts in the second substrate and level with the surface of the substrate; forming a metal layer over the substrate, preferably of a different metal than the metal contacts; patterning the metal layer to form vias; forming a first layer of dielectric material on the surface of the substrate over the exposed portions of the metal contacts and around the metal vias; forming a further metal layer over the first layer of dielectric material and the metal vias, preferably using a different metal than used for the metal vias; patterning the further metal layer into metal interconnects; and depositing a second layer of dielectric material over the exposed portions of the first layer of dielectric material and around the metal interconnects. If desired, the steps of forming the vias and the layer of metal interconnects (as well as the associated dielectric layers) may be repeated as many times as desired or needed to form the desired number of metal interconnect layers for the needed wiring structure. In a preferred embodiment, over the uppermost metal layer is formed a layer of low melting alloy material (solder) prior to the step of patterning this metal layer to facilitate the electrical connection of the metal interconnect structure to low melting alloyable material (solder) formed over a corresponding structure of integrated circuit (semiconductor) devices formed on a semiconductor substrate.

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